Patents by Inventor Mrinal Das

Mrinal Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040207549
    Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.
    Type: Application
    Filed: April 29, 2004
    Publication date: October 21, 2004
    Inventors: Prakash Easwaran, Mrinal Das
  • Patent number: 6804291
    Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: October 12, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Prakash Easwaran, Mrinal Das
  • Publication number: 20040100321
    Abstract: A system for signal boosting includes a capacitance boosting component that contains a first and second transistor and a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The system also includes a third transistor operable to receive a clock signal. A drain of the third transistor is electrically connected to the positive terminal of the capacitor. A fourth transistor is operable to receive an inverse of the clock signal. A drain of the fourth transistor is electrically connected to the positive terminal of the capacitor. The system further includes a boost component electrically connected to the capacitance boosting component wherein an output of the boost component is within a selected boost voltage range.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Mrinal Das
  • Publication number: 20030119472
    Abstract: By implementing the sampling process at an AC ground node, rather than at a signal side, and adding a gated transistor (610 and 620) in the signal path, the present invention reduces the interdependency between gain and linearity in a switched capacitor mixer circuit, supplies higher power without sacrificing area and simplifies the implementation of the RF switch. Charge boosting circuitry (630) allows a reduction in the effective size of a series switch (610 and 620) that follows a transconductance element (115).
    Type: Application
    Filed: April 16, 2002
    Publication date: June 26, 2003
    Inventor: Mrinal Das