Abstract: A computing device including a hardware accelerator. The hardware accelerator includes a generalized matrix-vector multiplication (GEMV) circuit configured to compute a product vector over a plurality of streaming iterations. At each of the streaming iterations, the GEMV circuit receives an input vector element and an input matrix row. The GEMV circuit multiplies the input vector element by input matrix elements included in the input matrix row to obtain an intermediate product row. The GEMV circuit adds the intermediate product row to a current-iteration row sum. The product vector is equal to the current-iteration row sum computed in a final streaming iteration. The GEMV circuit transmits the product vector as a streaming output to a post-processing circuit included in the hardware accelerator. The post-processing circuit performs a vector processing operation on the product vector to compute vector processing result, and outputs the vector processing result.

Abstract: A computing device including memory storing a mixed-precision tensor. The mixed-precision tensor includes one or more first tensor regions within which first tensor elements have a first precision and one or more second tensor regions within which second tensor elements have a second precision. The memory further stores a precision map indicating the first and second tensor regions. The computing device further includes a hardware accelerator configured to receive the precision map and the one or more first tensor regions, as indicated by the precision map, and perform a tensor processing operation on the one or more first tensor regions in the first precision. The hardware accelerator receives the one or more second tensor regions, as indicated by the precision map, and performs the tensor processing operation on the one or more second tensor regions in the second precision. The hardware accelerator stores a combined tensor processing output.

Abstract: According to one general aspect, an apparatus may include execution unit circuits, each configured to access one or more pieces of data. The apparatus may include local register file circuits, each associated with a respective execution unit circuit and each configured to store data. The apparatus may include a main register circuit. The main register circuit may include a main register file circuit configured to store data. The main register circuit may include a local index register circuit configured to map an index supplied by the main register file circuit to a storage location in the local register file circuits. The main register circuit may be configured to: receive from a control circuit a request to access the storage location of the specified data, and supply a target local register file circuit with the target local register file circuit's storage location of the specified data.

Abstract: According to one general aspect, an apparatus may include execution unit circuits, each configured to access one or more pieces of data. The apparatus may include local register file circuits, each associated with a respective execution unit circuit and each configured to store data. The apparatus may include a main register circuit. The main register circuit may include a main register file circuit configured to store data. The main register circuit may include a local index register circuit configured to map an index supplied by the main register file circuit to a storage location in the local register file circuits. The main register circuit may be configured to: receive from a control circuit a request to access the storage location of the specified data, and supply a target local register file circuit with the target local register file circuit's storage location of the specified data.