Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

Abstract: A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

Abstract: Systems and method for synchronizing access to buffered data are disclosed. In such a method, video data is buffered in a frame buffer memory by a producer device. A write level indicator is provided to a synchronizer by the producer device. A read level indicator is provided to the synchronizer by a consumer device. The synchronizer compares the write level indicator with the read level indicator to determine a difference. The consumer device is informed by the synchronizer when the difference meets a sub-frame threshold. The consumer device reads the buffered data from the frame buffer memory on a sub-frame-by-sub-frame basis responsive to the informing.

Abstract: A circuit for enabling the communication of data in a communication link associated with a data communication network is described. The circuit comprises a data generation circuit configured to receive a plurality of data streams and generate an output data stream; a control signal generator configured to generate synchronization headers; a serializer circuit configured to receive the output data stream from the data generation circuit and the synchronization headers from the control signal generator, wherein the serializer circuit generates, at an output, an output data signal having data of the output data stream and the synchronization headers; and a control circuit configured to control the data generation circuit and the control signal generator, wherein the control circuit enables a selection of the synchronization headers of the output data signal to enable channel alignment of the communication link.

Abstract: Methods and circuits are disclosed for configuring an integrated circuit (IC) to implement a system design. In an example implementation, boot ROM code is executed on the processor circuit. The execution of the boot ROM code causes the processor circuit to determine settings used by the system design for communicating data via a communication circuit on the IC. The communication circuit is configured by the processor circuit according to the determined settings. In response to receiving one or more boot images by the processor circuit, via the configured communication circuit configured according to the determined settings, boot images are executed by the processor circuit. The execution of the boot images causes the processor circuit to configure the IC to implement the system design. During operation of the system design on the IC, data is communicated via the communication circuit configured according to the determined settings.

Abstract: An integrated circuit (IC) that includes a processor circuit can be booted by receiving, using a storage interface circuit of the IC, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the IC to configure a bus interface module that is designed to communicate with a host device over a communication bus that links multiple devices and the IC. Using the bus interface module, a second boot image is received from the memory of the host device to a memory of the IC. The IC is booted by executing the second boot image.

Abstract: An integrated circuit (IC) that includes a processor circuit can be booted by receiving, using a storage interface circuit of the IC, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the IC to configure a bus interface module that is designed to communicate with a host device over a communication bus that links multiple devices and the IC. Using the bus interface module, a second boot image is received from the memory of the host device to a memory of the IC. The IC is booted by executing the second boot image.

Abstract: Circuits are provided for synchronizing serial communication channels having respective receivers, of which one is a master receiver. Each receiver includes a FIFO buffer and a synchronizing element. The FIFO buffer is written periodically with characters received from the serial communication channel of the receiver, and the FIFO buffer is read periodically, except between the start and end of synchronization of the receiver. The start of synchronization of the master receiver is generated from the timing of reading a channel bonding character from the FIFO buffer of the master receiver. The start of synchronization of each receiver other than the master receiver is generated after the start of the master receiver and in response to reading a channel bonding character from the FIFO buffer of the receiver. The end of synchronization of the receivers is generated a time interval after the start of the master receiver.