Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency.

Abstract: An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Abstract: A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency.

Abstract: An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Abstract: An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.

Abstract: Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.