Patents by Inventor Mu Chen
Mu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11616135Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.Type: GrantFiled: April 8, 2020Date of Patent: March 28, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11608319Abstract: A compound represented by Formula (I), a pharmaceutically acceptable salt or ester, hydrate, solvate or crystalline form thereof is provided: The compound represented by Formula (I) is a ?-amino acid derivative, and in Formula (I) X is a single bond or O; Y is NH or C?O; Z is C?O, C?S, NH, W is C or N; A is a single bond, O, OH, OCH2, a heterocycle or N3; R1 is H or F; R2 is H, F, OH, CF3, CH2OH, CHO or R3 is H; n is 0 or 1; and m is 0 or 1.Type: GrantFiled: December 10, 2020Date of Patent: March 21, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Wei Fu, Chih-Peng Liu, Yi-Hsun Chen, Chia-Mu Tu, Chiu-Lien Hung
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Patent number: 11600727Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.Type: GrantFiled: June 4, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
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Publication number: 20230062824Abstract: The present invention discloses a holder carrying thereon a sensor to measure a physiological signal of an analyte in a biological fluid, wherein the sensor has a signal detection end and a signal output end, and the holder includes an implantation hole being a channel for implanting the sensor and containing a part of the sensor, a fixing indentation containing the sensor, a filler disposed in the fixing indentation to retain the sensor in the holder, and a blocking element disposed between the implantation hole and the fixing indentation to hold the sensor in the holder and restrict the filler in the fixing indentation.Type: ApplicationFiled: October 18, 2022Publication date: March 2, 2023Inventors: Chun-Mu Huang, Chieh-Hsing Chen
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Patent number: 11568850Abstract: A noise cancellation circuit includes: a first filter circuit for filtering a first input signal according to a first filter coefficient to generate a first filtered signal; a signal processing circuit for generating a feedback signal according to a second input signal and an audio signal; a second filter circuit for filtering the feedback signal according to a second filter coefficient to generate a second filtered signal; a first multiplication circuit for multiplying the first filtered signal by a first scale to generate a first intermediate signal; a second multiplication circuit for multiplying the second filtered signal by a second scale to generate a second intermediate signal; a first adder circuit for adding the first intermediate signal to the second intermediate signal to generate a noise cancellation signal; and a second adder circuit for adding the noise cancellation signal to the audio signal to generate an output signal.Type: GrantFiled: December 15, 2021Date of Patent: January 31, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Mu-Chen Wu
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Patent number: 11563088Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: GrantFiled: December 10, 2019Date of Patent: January 24, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20230020271Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 11557666Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.Type: GrantFiled: November 22, 2020Date of Patent: January 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20230007831Abstract: The disclosure relates to a method for warehouse storage-location monitoring, a computer device, and a storage medium. The method includes the following. Video data of a warehouse storage-location area is obtained, and a target image corresponding to the warehouse storage-location area is obtained based on the video data, where the warehouse storage-location area includes an area of a storage-location and an area around the storage-location. The target image is detected based on a category detection model, to determine a category of each object appearing in the target image, where the category includes at least one of: human, vehicle, or goods. A detection result is obtained by detecting a status of each object based on the category of each object, where the detection result includes at least one of: whether the human enters the warehouse storage-location area, vehicle status information, or storage-location inventory information.Type: ApplicationFiled: July 1, 2022Publication date: January 12, 2023Applicant: VisionNav Robotics (Shenzhen) Co., Ltd.Inventors: Bingchuan YANG, Yujie LU, Mu FANG, Luyang LI, Peng CHEN
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Publication number: 20220413916Abstract: Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Chandra Gurram, Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio, Shuai Mu, Guei-Yuan Lueh, Supratim Pal
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Publication number: 20220416068Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20220402895Abstract: The present invention relates, in general terms, to a method of synthesising compounds and a system for synthesising compounds. The method and system can be automated. The method of synthesising a compound includes providing a solid support in fluid communication with a computer-controlled flow system, covalently bonding a first precursor to the solid support, performing at least one reaction, and cleaving the compound from the solid support.Type: ApplicationFiled: October 22, 2020Publication date: December 22, 2022Inventors: Jie WU, Saif A. KHAN, Chenguang LIU, Wenbin WU, Weihao CHEN, Mu WANG, Jiaxun XIE
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Patent number: 11532695Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.Type: GrantFiled: September 22, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Mu Yin, Hung-Chao Kao, Hsiang-Ku Shen, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220396431Abstract: A method for determining material-cage stacking, a computer device, and a storage medium are provided. The method includes the following. A material-cage image is obtained by photographing a first stacking apparatus of a first material cage and a second stacking apparatus of a second material cage. The stacking apparatuses of the two material cages in the material-cage image can be recognized respectively with two detection models. The first stacking result is obtained by obtaining location information of the stacking apparatuses of the two material cages with the first detection model, and the second stacking result is obtained with the second detection model.Type: ApplicationFiled: June 6, 2022Publication date: December 15, 2022Applicant: VisionNav Robotics (Shenzhen) Co., Ltd.Inventors: Peng CHEN, Luyang LI, Mu FANG, Yujie LU, Fan ZHENG, Bingchuan YANG
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Patent number: 11517229Abstract: A biosensing device includes a sensor module and an electric signal transducer. The sensor module includes a biosensor adapted for measuring a biosignal of a host, and a fixed seat including a conducting member that is electrically connected to the biosensor. The electric signal transducer is for receiving and sending the biosignal measured by the biosensor, is coupled to the sensor module, and includes an electric signal unit electrically connected to the conducting member, and a battery connected to the electric signal unit. The electric signal unit has two electrical contacts that cooperatively define a switch. The battery provides power supply to the biosensor when the electric signal transducer is coupled to the sensor module.Type: GrantFiled: May 27, 2020Date of Patent: December 6, 2022Assignee: BIONIME CORPORATIONInventors: Chun-Mu Huang, Chieh-Hsing Chen
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Patent number: 11521731Abstract: A charging device for a physiological signal transmitter is disclosed, wherein the physiological signal transmitter is to receive and externally transmit a physiological signal from a subcutaneous tissue of a living body, and has a first electrical connecting port. The charging device comprises a transmitter placing seat, a charging module and a locking module. The transmitter placing seat includes a bearing surface, and a first opening. The bearing surface disposes thereon the physiological signal transmitter; and the first opening aligns therewith the first electrical connecting port of the physiological signal transmitter. The charging module includes a second electrical connecting port, a third electrical connecting port and a circuit assembly. The second electrical connecting port is disposed in the first opening and moveable between a first position and a second position. The third electrical connecting port is for connecting thereto a power source.Type: GrantFiled: January 8, 2021Date of Patent: December 6, 2022Assignee: BIONIME CORPORATIONInventors: Chieh-Hsing Chen, Chun-Mu Huang
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Publication number: 20220376079Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
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Publication number: 20220377444Abstract: A speaker includes a rubber cabinet, a driver, and a plastic connection ring. The rubber cabinet is fixed to a case of an electronic device. The rubber cabinet accommodates the driver, and the plastic connection ring is connected between the rubber cabinet and the driver. Moreover, the plastic connection ring surrounds the driver, and the rubber cabinet surrounds the plastic connection ring.Type: ApplicationFiled: June 4, 2021Publication date: November 24, 2022Inventors: Mu-Heng TSAI, Yin-Chang CHENG, Chia-Chen CHEN, Chi-Zen PENG
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Publication number: 20220376081Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: I-Chih CHEN, Ru-Shang HSIAO, Ching-Pin LIN, Chih-Mu HUANG, Fu-Tsun TSAI
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Patent number: 11508818Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: GrantFiled: October 21, 2021Date of Patent: November 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang