Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.

Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a carrier having at least a semiconductor chip disposed thereon, the semiconductor chip having a first surface attached to the carrier, and an opposite second surface having a plurality of first conductive elements thereon; disposing an interposer on the first conductive elements, wherein the interposer has opposite third and fourth surfaces, the interposer is disposed on the first conductive elements via the third surface, and a plurality of conductive posts are embedded in the interposer and electrically connected to the third surface; forming an encapsulant on the carrier for encapsulating the semiconductor chip and the interposer; removing a portion of the encapsulant from the upper surface thereof and a portion of the interposer from the fourth surface thereof to expose ends of the conductive posts; and removing the carrier, thereby improving the connection quality between the semiconductor chip and the i

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.