Patents by Inventor Mu-kyeng Jung
Mu-kyeng Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9397234Abstract: A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region.Type: GrantFiled: April 24, 2015Date of Patent: July 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-min Choi, Ju-youn Kim, Hyun-jo Kim, Mu-kyeng Jung
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Publication number: 20160079446Abstract: A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region.Type: ApplicationFiled: April 24, 2015Publication date: March 17, 2016Inventors: Hyun-min CHOI, Ju-youn KIM, Hyun-jo KIM, Mu-kyeng JUNG
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Patent number: 7928002Abstract: A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.Type: GrantFiled: March 3, 2009Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-kyeng Jung, Sun-jung Lee, Ki-chul Park
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Patent number: 7679123Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.Type: GrantFiled: March 12, 2007Date of Patent: March 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-jun Oh, Kyung-tae Lee, Mu-kyeng Jung
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Publication number: 20090227101Abstract: A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.Type: ApplicationFiled: March 3, 2009Publication date: September 10, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Mu-kyeng JUNG, Sun-jung LEE, Ki-chul PARK
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Patent number: 7576613Abstract: A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.Type: GrantFiled: February 23, 2007Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-Kyeng Jung, Soon-Kyun Shin
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Patent number: 7560332Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: GrantFiled: April 10, 2007Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Wan-Jae Park, Jeong-Hoon Ahn, Kyung-Tae Lee, Mu-Kyeng Jung, Yong-Jun Lee, Il-Goo Kim, Soo-Geun Lee
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Patent number: 7446607Abstract: A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.Type: GrantFiled: May 3, 2007Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-Kyeng Jung, Jae-Whui Kim, Bai-Sun Kong
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Publication number: 20080032483Abstract: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern.Type: ApplicationFiled: October 5, 2007Publication date: February 7, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Hyuk-Ju Ryu, Heon-Jong Shin, Hee-Sung Kang, Choong-Ryul Ryou, Mu-Kyeng Jung, Kyung-Soo Kim
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Publication number: 20080023761Abstract: Semiconductor devices and methods of fabricating the same are provided. According to an example embodiment, a semiconductor device may include an active region disposed in a substrate and having first conductivity type impurity ions, a gate electrode crossing on the active region, a source region disposed within the active region at one a first side of the gate electrode, a drain region disposed within the active region at the a second side of the gate electrode, a source lightly doped drain (LDD) region disposed within the active region, extending toward the gate electrode from the source region, and having second conductivity type impurity ions, a drain LDD region disposed within the active region, extending toward the gate electrode from the drain region, and having the second conductivity type impurity ions in a concentration higher than the source LDD region, and a first halo region disposed within the active region, surrounding the source LDD region, and having the first conductivity type impurity ions.Type: ApplicationFiled: June 28, 2007Publication date: January 31, 2008Inventors: Mu-Kyeng Jung, Xiao Quan Wang, Bai-Sun Kong
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Publication number: 20080007338Abstract: A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.Type: ApplicationFiled: May 3, 2007Publication date: January 10, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Mu-Kyeng Jung, Jae-Whui Kim, Bai-Sun Kong
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Patent number: 7285831Abstract: A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.Type: GrantFiled: July 12, 2005Date of Patent: October 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-kyeng Jung, Hee-sung Kang, Hyuk-ju Ryu, Woo-young Chung, Kyung-soo Kim
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Publication number: 20070200632Abstract: A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.Type: ApplicationFiled: February 23, 2007Publication date: August 30, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Mu-Kyeng Jung, Soon-Kyun Shin
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Publication number: 20070184610Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: ApplicationFiled: April 10, 2007Publication date: August 9, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-woo Lee, Wan-jae Park, Jeong-hoon Ahn, Kyung-tae Lee, Mu-kyeng Jung, Yong-jun Lee, Il-goo Kim, Soo-geun Lee
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Publication number: 20070145452Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.Type: ApplicationFiled: March 12, 2007Publication date: June 28, 2007Inventors: Byung-jun Oh, Kyung-tae Lee, Mu-kyeng Jung
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Patent number: 7229875Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: GrantFiled: October 16, 2003Date of Patent: June 12, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Wan-jae Park, Jeong-hoon Ahn, Kyung-tae Lee, Mu-kyeng Jung, Yong-jun Lee, Il-goo Kim, Soo-geun Lee
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Patent number: 7208791Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.Type: GrantFiled: June 28, 2005Date of Patent: April 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-jun Oh, Kyung-tae Lee, Mu-kyeng Jung
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Publication number: 20060240636Abstract: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern.Type: ApplicationFiled: February 21, 2006Publication date: October 26, 2006Inventors: Hyuk-Ju Ryu, Heon-Jong Shin, Hee-Sung Kang, Choong-Ryul Ryou, Mu-Kyeng Jung, Kyung-Soo Kim
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Publication number: 20060027876Abstract: A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.Type: ApplicationFiled: July 12, 2005Publication date: February 9, 2006Inventors: Mu-kyeng Jung, Hee-sung Kang, Hyuk-ju Ryu, Woo-young Chung, Kyung-soo Kim
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Publication number: 20050247968Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.Type: ApplicationFiled: June 28, 2005Publication date: November 10, 2005Inventors: Byung-jun Oh, Kyung-tae Lee, Mu-kyeng Jung