Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

Abstract: A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width.

Abstract: Disclosed are a video interaction method, a terminal, a server, and a system. The method includes: receiving a video microphone-connection invitation transmitted by a first terminal, the video microphone-connection invitation carrying at least one terminal identifier; transmitting the video microphone-connection invitation to a second terminal corresponding to the terminal identifier; after receiving an accept response returned by the second terminal, granting the second terminal a video publishing right, and establishing a microphone-connection session connection between the first terminal and the second terminal; receiving video data published by the first terminal and video data published by the second terminal, wherein the video data published by the first terminal and the video data published by the second terminal are displayed on the same window interface respectively in the first terminal and the second terminal.

Abstract: An integrated circuit includes a first semiconductor fin, a first epitaxy structure, and at least two first dielectric fin sidewall structures. The first epitaxy structure is disposed on the first semiconductor fin. The first dielectric fin sidewall structures are disposed on opposite sidewalls of the first epitaxy structure. The first dielectric fin sidewall structures have different heights.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are disclosed herein. The semiconductor structure includes a substrate, a strain-inducing layer and an epitaxy structure. The strain-inducing layer is disposed on the substrate, and the epitaxy structure is embedded in the strain-inducing layer and not in contact with the substrate.

Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for handling faults in a distributed key-value storage system. One of the methods includes receiving an indication that a machine storing a primary replica of a first replication chain is inactive, in response to receiving the indication, generating a concatenated replica comprising a first replica of the first replication chain and a second replica of a second replication chain, the second replication chain comprising replicas of a second key segment, the second key segment being adjacent to the first key segment in the multiple key segments of the plurality of keys, and providing, to another machine in the ordered sequence of machines, a notification of availability of the concatenated replica.

Abstract: An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained materials disposed on each of the plurality of the fin structures; a plurality of cap layers individually formed on each of the plurality of first strained materials, wherein at least two cap layers are connected to each other; a second strained material disposed on the at least two cap layers which are connected to each other.

Abstract: Disclosed are methods, compositions and kits for the isolation of exosomes from biological fluids and tissues. Volume-excluding polymers are used to precipitate exosomes from biological samples thereby allowing exosome isolation by low-speed (benchtop) centrifugation or filtration. Further fractionation of exosomes after precipitation is also described.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.

Abstract: A method for reducing release of resistance genes during sludge anaerobic treatment includes controlling concentration of to-be-treated sludge in a concentration tank to be 12-20 g/L by sedimentation under gravity. The concentrated sludge is transferred to a supersonic pre-treatment device to proceed with supersonic pre-treatment. The supersonic pre-treatment is conducted for 5-30 minutes at a power of 0.1-0.5 kW and a frequency of 10-40 kHz. The pre-treated sludge is then transferred to an anaerobic treatment device for anaerobic treatment. The anaerobic treatment is conducted for 4-12 days at a temperature of 20-37° C. The release amount of resistance genes in the residual sludge and the supernatant liquid in the anaerobic treatment device is detected. A feedback dosage of an alkali liquid is fed into the anaerobic treatment device according to the release amount of the resistance genes, controlling a pH value to be 9.0-11.0 during the anaerobic treatment.

Abstract: An input method editor (IME) configured to provide language assistance across a plurality of applications is disclosed. In one example, the IME is adapted for use by English-as-a-second-language (ESL) users. In a specific example, language assistance may be provided by first detecting a need to suggest a substitute word to a user who is typing within an application. The detection may be based on a probability that a current word is in error. If a need is detected, a suggestion may be obtained for the word, such as from a cloud linguistic service or from a local lexicon and language-model, if network connectivity is poor. Once obtained, the suggestion may be displayed to the user in a non-intrusive manner by user interface element(s). Interaction with the user allows the user to accept or reject the suggestion, and perform other functions, such as relocating user interface elements utilized by the display.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.