Patents by Inventor Mu-Shan Lin
Mu-Shan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791834Abstract: A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.Type: GrantFiled: February 15, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai
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Publication number: 20230261668Abstract: A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: YU-JIE HUANG, MU-SHAN LIN, CHIEN-CHUN TSAI
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Patent number: 10644865Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry.Type: GrantFiled: October 24, 2018Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Chun Yang, Mu-Shan Lin, Wen-Hung Huang
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Patent number: 10277215Abstract: Digital controlled delay lines are provided. A digital controlled delay line includes a plurality of delay cells coupled in a chain forming a propagation path to propagate an input signal and to delay the input signal by a delay time. The propagation path is formed when a single delay cell is operated in a feedback mode, the delay cells previous to the single delay cell in the chain are operated in a propagation mode, a subsequent delay cell following the single delay cell in the chain is operated in a standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in an idle mode.Type: GrantFiled: April 28, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Ting Tsai, Chien-Chun Tsai, Mu-Shan Lin, Wen-Hung Huang, Yu-Chi Chen
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Publication number: 20190058573Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry.Type: ApplicationFiled: October 24, 2018Publication date: February 21, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Chun YANG, Mu-Shan LIN, Wen-Hung HUANG
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Patent number: 10164758Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry.Type: GrantFiled: December 21, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semicondcutor Manufacturing Co., Ltd.Inventors: Shu-Chun Yang, Mu-Shan Lin, Wen-Hung Huang
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Publication number: 20180316337Abstract: Digital controlled delay lines are provided. A digital controlled delay line includes a plurality of delay cells coupled in a chain forming a propagation path to propagate an input signal and to delay the input signal by a delay time. The propagation path is formed when a single delay cell is operated in a feedback mode, the delay cells previous to the single delay cell in the chain are operated in a propagation mode, a subsequent delay cell following the single delay cell in the chain is operated in a standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in an idle mode.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Meng-Ting TSAI, Chien-Chun TSAI, Mu-Shan LIN, Wen-Hung HUANG, Yu-Chi CHEN
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Publication number: 20180152279Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry.Type: ApplicationFiled: December 21, 2016Publication date: May 31, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Chun YANG, Mu-Shan Lin, Wen-Hung Huang
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Patent number: 9571073Abstract: An integrated circuit includes a clock source tier and at least two clock distribution tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit. Each of the at least two clock distribution tiers includes a clock distribution circuit. Each clock distribution circuit includes at least one pair of cross-coupled inverters.Type: GrantFiled: March 3, 2015Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Mu-Shan Lin
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Patent number: 9520867Abstract: A clock generating circuit includes a clock generator, a first clock tree, a second clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal. The first clock tree includes a driver cell configured to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The second clock tree includes a driver cell configured to generate a third output clock signal based on the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.Type: GrantFiled: May 28, 2015Date of Patent: December 13, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Mu-Shan Lin
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Patent number: 9331845Abstract: A system and method is disclosed for adjusting for timing variations between a data signal and an associated data read signal being transmitted from a first chip and received on a second chip.Type: GrantFiled: June 29, 2012Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Chun Yang, Wei Chih Chen, Mu-Shan Lin
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Publication number: 20150263716Abstract: A clock generating circuit includes a clock generator, a first clock tree, a second clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal. The first clock tree includes a driver cell configured to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The second clock tree includes a driver cell configured to generate a third output clock signal based on the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.Type: ApplicationFiled: May 28, 2015Publication date: September 17, 2015Inventor: Mu-Shan LIN
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Publication number: 20150180456Abstract: An integrated circuit includes a clock source tier and at least two clock distribution tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit. Each of the at least two clock distribution tiers includes a clock distribution circuit. Each clock distribution circuit includes at least one pair of cross-coupled inverters.Type: ApplicationFiled: March 3, 2015Publication date: June 25, 2015Inventor: Mu-Shan LIN
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Patent number: 9059691Abstract: A duty cycle detection and correction circuit includes a clock generator, a clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal, and the first clock signal and the second clock signal have a predetermined phase difference. The clock tree is configured to receive the first clock signal and the second clock signal, to generate a first output clock signal based on the first clock signal and the set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.Type: GrantFiled: March 15, 2013Date of Patent: June 16, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Mu-Shan Lin
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Patent number: 9000823Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.Type: GrantFiled: September 12, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Mu-Shan Lin
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Publication number: 20150070067Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Mu-Shan Lin
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Patent number: 8847655Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.Type: GrantFiled: May 22, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Mu-Shan Lin
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Publication number: 20140184292Abstract: A duty cycle detection and correction circuit includes a clock generator, a clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal, and the first clock signal and the second clock signal have a predetermined phase difference. The clock tree is configured to receive the first clock signal and the second clock signal, to generate a first output clock signal based on the first clock signal and the set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.Type: ApplicationFiled: March 15, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Mu-Shan Lin
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Publication number: 20140003551Abstract: A system and method is disclosed for adjusting for timing variations between a data signal and an associated data read signal being transmitted from a first chip and received on a second chip.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Chun YANG, Wei Chih CHEN, Mu-Shan LIN
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Publication number: 20130314146Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.Type: ApplicationFiled: May 22, 2012Publication date: November 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Mu-Shan Lin