Patents by Inventor Mu-Sheng Liao

Mu-Sheng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147606
    Abstract: An electronic device includes a first substrate structure, multiple electronic elements and a second substrate structure. The first substrate structure includes a first substrate. The electronic elements are disposed on the first substrate. The second substrate structure is coupled to the first substrate structure. The second substrate structure includes a second substrate, a protection circuit, a driving circuit and a bonding pad. The protection circuit is disposed on the second substrate. The driving circuit is disposed on the second substrate and configured to drive at least a part of the electronic elements. The bonding pad is disposed on the second substrate. The protection circuit is respectively coupled to the bonding pad and the driving circuit. The electronic device may reduce the damage caused by electrostatic discharge or reduce the impact of the bonding process of the bonding pad on signal conduction.
    Type: Application
    Filed: September 14, 2023
    Publication date: May 2, 2024
    Applicant: Innolux Corporation
    Inventors: Mu-Fan Chang, Yi-Hua Hsu, Hung-Sheng Liao, Min-Hsin Lo, Ming-Chun Tseng, Ker-Yih Kao
  • Publication number: 20070103179
    Abstract: A socket base adaptable to a load board for testing semiconductor devices is disclosed. The socket base includes a first fixing element having coupling plates, a probe element, and a second fixing element, which are detachable and combinable. Accordingly, the procedure for replacing the probe element is simplified, time is reduced, and efficiency is increased.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 10, 2007
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: SHOU-NAN TSAI, MU-SHENG LIAO
  • Patent number: 7094068
    Abstract: A load board for packaged IC testing. The load board with predetermined testing circuit thereon has bonding pad areas on its surface. A plurality of bonding pads is formed on the bonding pad areas, each of which is disposed corresponding to a lead of a packaged IC for testing connection, such as a quad flat packaged IC (QFP), a dual inline packaged IC (DIP) or a small outline packaged IC (SOP). The bonding pads on the load board connect the leads of the testing IC directly during IC testing, thus the conventional test socket between a conventional load board and a packaged IC is omitted.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: August 22, 2006
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ching-Jung Huang, Hsiu-Chu Chou, Mu-Sheng Liao, Fu-Tsai Chen, Pao-Chuan Kuo
  • Publication number: 20050037638
    Abstract: A load board for packaged IC testing. The load board with predetermined testing circuit thereon has bonding pad areas on its surface. A plurality of bonding pads is formed on the bonding pad areas, each of which is disposed corresponding to a lead of a packaged IC for testing connection, such as a quad flat packaged IC (QFP), a dual inline packaged IC (DIP) or a small outline packaged IC (SOP). The bonding pads on the load board connect the leads of the testing IC directly during IC testing, thus the conventional test socket between a conventional load board and a packaged IC is omitted.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 17, 2005
    Inventors: Ching-Jung Huang, Hsiu-Chu Chou, Mu-Sheng Liao, Fu-Tsai Chen, Pao-Chuan Kuo
  • Publication number: 20040075091
    Abstract: A semiconductor package device testing apparatus includes a conductive component, a first main body, a second main body, a pressing member, and a heating component. The conductive component has a plurality of conductive portions electrically connect with the pins of the semiconductor package device and disposed at one side of the first main body. The second main body is disposed at the other side of the first main body. In addition, the first main body has a first opening to define a space for receiving the semiconductor package device. The semiconductor package device is disposed within the first opening by the pressing member. The pressing member connects to the second main body through a second opening of the second main body. The heating component mounts on the first main body to heat the semiconductor package device.
    Type: Application
    Filed: December 18, 2002
    Publication date: April 22, 2004
    Inventors: Ching-jung Huang, Hsiu-Chu Chou, Mu-Sheng Liao, Cheng-ji Yu, Kuo-Hsiung Hong
  • Publication number: 20030164716
    Abstract: An alignment apparatus for an integrated circuit (IC) test handler is disclosed. The alignment apparatus of the present invention installs a plurality of first guide pins and a plurality of second guide pins on a load board stiffener, and the first and second guide pins penetrate a load board and a surface mount matrix (SMM) frame member used for fastening a SMM sequentially from the backsides of load board and SMM frame member. When an IC device packaged by the ball grid array (BGA) method is in an electrical test, the present invention can shorten the working distance of a test arm of the IC test handler for enhancing the stability of testing process, thereby promoting the testing yield. Furthermore, with a shorter working distance, the output force from the test arm is smaller, so that the force acted on solder balls located at the bottom of the BGA device is smaller, thereby prolonging the service life of SMM contacting the solder balls.
    Type: Application
    Filed: March 4, 2002
    Publication date: September 4, 2003
    Inventors: Yi-Chang Hsieh, Mu-Sheng Liao, Ching-Jung Huang
  • Patent number: 6498505
    Abstract: A testing jig for semiconductor components, mainly comprising a main jig body, wherein on its bottom is provided with a retrieving head. While on the center of the bottom of the retrieving head is provided with a concave space, around which is arranged a plurality of air holes which are connected with the internal airways and also connected with the air inlet on the top of the main body. Furthermore, on the bottom of the main jig body is provided with two buffer blocks on opposite sides, which can prevent the chip on the center of the base board from being contacted with external force or foreign objects in the process of retrieving the base board during testing.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: December 24, 2002
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Mu-Sheng Liao, Wei-Feng Lin, Chen-Wen Tsai, Ching-Jung Huang
  • Publication number: 20020125902
    Abstract: The present invention relates to a testing jig for semiconductor components, mainly comprising a main jig body, wherein on its bottom is provided with a retrieving head. While on the center of the bottom of the retrieving head is provided with a concave space, around which is arranged a plurality of air holes which are connected with the internal airways and also connected with the air inlet on the top of the main body. Furthermore, on the bottom of the main jig body is provided with two buffer blocks on opposite sides, which can prevent the chip on the center of the base board from being contacted with external force or foreign objects in the process of retrieving the base board during testing.
    Type: Application
    Filed: March 8, 2001
    Publication date: September 12, 2002
    Inventors: Mu-Sheng Liao, Wei-Feng Lin, Chen-Wen Tsai, Ching-Jung Huang
  • Patent number: 6444034
    Abstract: An apparatus for preventing electrostatic destruction of integrated circuits coats an electrostatic agent on surfaces of the integrated circuits to avoid accumulation of static electricity caused by dynamic contact friction. The apparatus comprises a belt, at least one motor, at least one spray nozzle, at least one dispenser or controller and at least one photo switch. The integrated circuits are placed on the belt. The motor drives the belt and therefore the integrated circuits step by step to the spray nozzle to coat the electrostatic agent on the surfaces of the integrated circuits. The controller controls the output rate of the electrostatic agent from the spray nozzle. The photo switch is connected to the spray nozzle and dispenser to detect the integrated circuits as they pass the spray nozzle.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: September 3, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Yi-Chang Hsieh, Lai-Fue Hsieh, Mu-Sheng Liao, Ching-Jung Huang
  • Patent number: 6287071
    Abstract: An apparatus is adapted for picking-up an integrated circuit component and is adapted to be connected to an air pump. The apparatus includes a retaining block formed with a first pipe hole and a washer receiving recess for receiving a washer. An air pipe is formed with a radially and outwardly extending rim flange at a junction of upper and lower pipe sections thereof. The lower pipe section extends sealingly through a second pipe hole in the washer and further through the first pipe hole such that the rim flange rests on top of the washer in the washer receiving recess, such that a distal lower end of the lower pipe section projects downwardly relative to the retaining block, and such that a distal upper end of the upper pipe section extends outwardly of the washer receiving recess and projects upwardly relative to the retaining block.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: September 11, 2001
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Lai-Fue Hsieh, Yi-Chang Hsieh, Ching-Jung Huang, Mu-Sheng Liao
  • Patent number: 6204676
    Abstract: A testing apparatus for testing a ball grid array (BGA) device, includes a movable carrier which has a top face recessed to form a cavity of square shape to receive the BGA device. A centering member is disposed at a center part of a cavity bottom face of the cavity to center a squarely looped array of voltage source solder balls formed at a bottom face of the BGA device, relative to the center part of the cavity bottom face. The centering member projects upward from the cavity bottom face to engage and prevent positional deviation of the squarely looped array of the voltage source solder balls when the BGA device is seated on the cavity bottom face. The testing apparatus further includes a testing circuit unit, a surface mount matrix disposed on top of the testing circuit unit, and a hollow frame member mounted on top of the surface mount matrix.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: March 20, 2001
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Yi-Chang Hsieh, Lai-Fue Hsieh, Mu-Sheng Liao
  • Patent number: 6075255
    Abstract: A contactor system is adapted for use when testing a ball grid array (BGA) device, and includes a conductive socket that is retained on a testing board and that establishes a ground connection therewith. The socket is formed with a receiving space adapted for receiving the BGA device therein. An insulating guide unit is mounted on the socket in the receiving space and is adapted to guide loading movement of the BGA device into the receiving space via an open top section of the latter and to prevent undesired electrical contact between the socket and the BGA device. A surface mount matrix is disposed on top of the testing board and is clamped between the socket and the testing board. The surface mount matrix is accessible via an open bottom section of the receiving space, and is adapted to contact solder balls on the BGA device directly so as to establish electrical connection between the BGA device and testing circuit layout on the testing board.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: June 13, 2000
    Assignee: Silicon Integrated Systems Company
    Inventors: Mu-Sheng Liao, Lai-Fue Hsieh, Yi-Chang Hsieh