Patents by Inventor Mu-Yi Lin
Mu-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11011419Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.Type: GrantFiled: March 26, 2020Date of Patent: May 18, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Publication number: 20200227316Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Patent number: 10629481Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.Type: GrantFiled: July 24, 2017Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Patent number: 9934925Abstract: Fuse structures and forming and operation methods thereof are disclosed. One of the fuse structures includes a dielectric strip and a fuse strip extending in different directions. The dielectric strip is sandwiched by a first conductive strip and a second conductive strip. The fuse strip is insulated from each of the first conductive strip and the second conductive strip and has a blowing region corresponding to the dielectric strip.Type: GrantFiled: November 16, 2015Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chou Tsai, Mu-Yi Lin, Tzy-Kuang Lee
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Publication number: 20170323827Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Patent number: 9716034Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.Type: GrantFiled: October 20, 2015Date of Patent: July 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Publication number: 20170140891Abstract: Fuse structures and forming and operation methods thereof are disclosed. One of the fuse structures includes a dielectric strip and a fuse strip extending in different directions. The dielectric strip is sandwiched by a first conductive strip and a second conductive strip. The fuse strip is insulated from each of the first conductive strip and the second conductive strip and has a blowing region corresponding to the dielectric strip.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Chia-Chou Tsai, Mu-Yi Lin, Tzy-Kuang Lee
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Publication number: 20160042992Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Patent number: 9190319Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.Type: GrantFiled: March 8, 2013Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Lin, Jhu-Ming Song, Mu-Yi Lin, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
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Publication number: 20140252621Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsuan-Han Lin, Jhu-Ming Song, Mu-Yi Lin, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
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Patent number: 6956254Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.Type: GrantFiled: December 1, 2003Date of Patent: October 18, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Tien Yang, Mu-Yi Lin, Yu-Wei Tseng, Min Ca, Yu-Hua Lee
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Publication number: 20050173799Abstract: A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.Type: ApplicationFiled: February 5, 2004Publication date: August 11, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Juan-Jann Jou, Yu-Hua Lee, Chin-Tien Yang, Chia-Hung Lai, Connie Hsu, Mu-Yi Lin, Min Cao, Chia-Yu Ku, Yuh-Da Fan
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Publication number: 20050116281Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.Type: ApplicationFiled: December 1, 2003Publication date: June 2, 2005Inventors: Chin-Tien Yang, Mu-Yi Lin, Yu-Wei Tseng, Min Cao, Yu-Hua Lee