Abstract: A dual-trajectory pedicle screw system includes an internally threaded sleeve and including first part and cylindrical second part, the first part being recessed to form a space, and the second part including projections on top; a main screw including a universal head and a first conic member, the universal head including first and second threaded holes, the first threaded hole being inclined at a first angle, the second threaded hole being inclined at a different second angle, bottom of the universal head being a convex and rotatably disposed in the space; and an auxiliary screw including external threads threadedly secured to the first or second threaded hole so that the auxiliary screw is secured to the main screw at the first or second angle with respect to the main screw, a second conic member extending downward from the external threads, and a fitting member on top of the external threads.

Abstract: A bandage structure includes a substrate, an elastic sheet, a plurality of adhesive elements, and a plurality of protective layers. The substrate includes a hollow portion and a plurality of adhesive portions. The hollow portion includes a plurality of first elongated holes that are arranged in one row parallel to a length direction of the substrate. The adhesive portions are located on two sides of the hollow portion and the elastic sheet is located on the substrate. The elastic sheet includes an extension portion and a plurality of attaching portions. The extension portion corresponds in position to the hollow portion and has a plurality of second elongated holes. The second elongated holes are arranged in one row parallel to a length direction of the elastic sheet. The first elongated holes and the second elongated holes are staggered with each other along a length direction of the bandage structure.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The doped regions are disposed in the substrate on each side of the stacked gate structure. The high stress material layers are disposed on the substrate to cover the doped regions. The high stress material layers can increase the mobility of the carriers in the doped regions and hence accelerate the operating speed of the device.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-FIN layers.

Abstract: An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

Abstract: Methods of Manufacturing a Nitride Trapping EEPROM Flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-FIN layers.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The doped regions are disposed in the substrate on each side of the stacked gate structure. The high stress material layers are disposed on the substrate to cover the doped regions. The high stress material layers can increase the mobility of the carriers in the doped regions and hence accelerate the operating speed of the device.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

Abstract: A non-volatile memory cell. The non-volatile memory cell comprises a substrate with a first conductive type, a gate structure, at least two source/drain regions with a second conductive type and a buried channel region with the second conductive type. The gate structure is located on the substrate, and the source/drain regions are located in the substrate adjacent to both sides of the gate structure. Further, the buried channel region is located under the gate structure in the substrate, wherein the buried channel region is separated from the source/drain regions.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.