Abstract: A controller for generating a control parameter of a feedback system may include a proportional path comprising a first selector configured to select one of a plurality of proportional signals to generate a proportional path output, wherein each of the proportional signals is based on a respective one of a plurality of error signals, each of the plurality of error signals associated with a respective regulated physical quantity, an integral path comprising a second selector configured to select one of a plurality of integral signals as a second selector output, wherein each of the integral signals is based on a respective one of the plurality of error signals and a single integrator configured to accumulate successive samples of the second selector output to generate an integral path output, and combiner logic configured to combine the proportional path output and the integral path output to generate the control parameter.

Abstract: Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

Abstract: A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path having an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

Abstract: Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

Abstract: A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

Abstract: A digital to analog convertor comprises an output line; first, second and third pluralities of capacitors; and first and second bridge capacitors. The first plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a first least significant bit capacitor of a first capacitance value. The second plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a second capacitor of the first capacitance value. The third plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a third capacitor of the first capacitance value. The first bridge capacitor bridges the output line between the first plurality of capacitors and the second plurality of capacitors. The second bridge capacitor bridges the output line between the second plurality of capacitors and the third plurality of capacitors.

Abstract: An amplifier capable of driving an analog load is provided. The amplifier can be constructed and arranged to operate as at least one circuit selected from the group consisting of a class D amplifier, voltage regulator, audio amplifier, servo amplifier, servo control, digital control, switching power supply, and switching power amplifier. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon an input signal (e.g., an analog input signal) to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses.

Abstract: An amplifier capable of driving an analog load is provided. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon a digital input signal to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses. The output stage is coupled to the pulse processing circuit and has first state wherein the output stage provides analog noise-shaped output energy pulses to a load and a second state where the output energy delivered is essentially zero. The feedback loop is coupled between the output stage and the SDM.

Abstract: A sigma delta modulator (SDM) data converter system is provided. The SDM data converter system comprises a signal path, a feedback signal path, and a multi-bit quantizer disposed in a feedforward path. The signal path receives an input signal to be processed. The feedback signal path provides a feedback signal that is subtracted from the input signal. The multi-bit quantizer is disposed in the feedforward path so as to receive the input signal after the feedback signal has been subtracted from it. Te multi-bit quantizer uses feedforward dynamic element matching (DEM) to spectrally shape mismatch errors in the SDM data conversion system and produce an output signal, wherein the output signal of the multi-bit quantizer is used for at least a portion of the feedback signal.

Abstract: A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).

Abstract: An amplifier capable of driving an analog load is provided. The amplifier can be constructed and arranged to operate as at least one circuit selected from the group consisting of a class D amplifier, voltage regulator, audio amplifier, servo amplifier, servo control, digital control, switching power supply, and switching power amplifier. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon an input signal (e.g., an analog input signal) to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses.

Abstract: An amplifier capable of driving an analog load is provided. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon a digital input signal to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses. The output stage is coupled to the pulse processing circuit and has first state wherein the output stage provides analog noise-shaped output energy pulses to a load and a second state where the output energy delivered is essentially zero. The feedback loop is coupled between the output stage and the SDM.

Abstract: A sigma delta modulator (SDM) data converter system is provided. The SDM data converter system comprises a signal path, a feedback signal path, and a multi-bit quantizer disposed in a feedforward path. The signal path receives an input signal to be processed. The feedback signal path provides a feedback signal that is subtracted from the input signal. The multi-bit quantizer is disposed in the feedforward path so as to receive the input signal after the feedback signal has been subtracted from it. Te multi-bit quantizer uses feedforward dynamic element matching (DEM) to spectrally shape mismatch errors in the SDM data conversion system and produce an output signal, wherein the output signal of the multi-bit quantizer is used for at least a portion of the feedback signal.

Abstract: A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).

Abstract: A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).

Abstract: An ultra-low voltage rail-to-rail operational transconductance amplifier (OTA) is based on a standard digital 0.18 ?m CMOS process. Techniques for designing a 0.8 volt fully differential OTA include bias and reference current generator circuits. To achieve rail-to-rail operation, complementary input differential pairs are used, where the bulk-driven technique is applied to reduce the threshold limitation of the MOSFET transistors. The OTA gain is increased by using auxiliary gain boosting amplifiers.