Patents by Inventor Mufeng Zhou

Mufeng Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240005977
    Abstract: The disclosed apparatus comprises a computing array comprising a plurality of computing modules, wherein each computing module comprises at least one storage cell, a reset switch, and a capacitor; the storage cell comprises at least one storage switch, and the storage switch comprises a storage control terminal, a storage detection terminal, and a storage terminal, the storage control terminal to receive a storage state voltage to adjust the impedance characteristic between the storage detection terminal and the storage terminal; the reset switch comprises a reset control terminal, a reset detection terminal, and a reset terminal, the reset control terminal to receive a reset voltage and the reset terminal is used to receive a reset state voltage. The disclosed apparatus also comprises a control module, which is used to control the computing array to perform at least one of a store operation, a read operation, and a compute operation.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 4, 2024
    Inventors: Xueqing LI, Guodong YIN, Yiming CHEN, Lingan CHEONG, Tianyu LIAO, Wenjun TANG, Mingyen LEE, Xirui DU, Zhonghao CHEN, Mufeng ZHOU, Chen WANG, Zekun YANG, Yongpan LIU, Huazhong YANG
  • Patent number: 11475927
    Abstract: The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 18, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Xueqing Li, Yiming Chen, Xiaoyang Ma, Mufeng Zhou, Yushen Fu, Yongpan Liu, Huazhong Yang