Patents by Inventor Muh-Ling Ger
Muh-Ling Ger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11621331Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.Type: GrantFiled: September 10, 2020Date of Patent: April 4, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Publication number: 20220254889Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.Type: ApplicationFiled: April 26, 2022Publication date: August 11, 2022Applicant: Semiconductor Components Industries, LLCInventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
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Patent number: 11411077Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.Type: GrantFiled: September 10, 2020Date of Patent: August 9, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Patent number: 11342424Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.Type: GrantFiled: April 13, 2020Date of Patent: May 24, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
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Publication number: 20220077282Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Applicant: Semiconductor Components Industries, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Publication number: 20220077290Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Applicant: Semiconductor Components Industries, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Publication number: 20210320178Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.Type: ApplicationFiled: April 13, 2020Publication date: October 14, 2021Applicant: Semiconductor Components Industries, LLCInventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
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Patent number: 6318174Abstract: A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).Type: GrantFiled: March 30, 2000Date of Patent: November 20, 2001Assignee: Motorola, IncInventors: John E. Schmiesing, Guang X. Li, Juergen A. Foerstner, Muh-Ling Ger, Paul L. Bergstrom, Frank A. Shemansky, Jr.
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Patent number: 6105428Abstract: A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).Type: GrantFiled: December 10, 1998Date of Patent: August 22, 2000Assignee: Motorola, Inc.Inventors: John E. Schmiesing, Guang X. Li, Juergen A. Foerstner, Muh-Ling Ger, Paul L. Bergstrom, Frank A. Shemansky, Jr.
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Patent number: 6087701Abstract: A semiconductor device (50) has a sensing element (30) and a transistor (40). The sensing element (30) is formed in a cavity (11) in a substrate (10). The sensing element (30) is formed in part using an epitaxial deposition process that fills the cavity (11) with a conductive material (18) such as polysilicon. A dielectric layer (17) is used to electrically isolate the sensing element (30) from the substrate (10).Type: GrantFiled: December 23, 1997Date of Patent: July 11, 2000Assignee: Motorola, Inc.Inventors: Paul L. Bergstrom, Muh-Ling Ger