Abstract: A recursive discrete Fourier transform (RDFT) of this invention uses an input-decimation technique to reduce the number of input sequences for a recursive-filter so as to decrease the computation cycle of the recursive-filter. Therefore, the time complexity of the RDFT can be minimized, namely, increasing the throughput of the RDFT.

Abstract: A recursive discrete Fourier transform (RDFT) of this invention uses an input-decimation technique to reduce the number of input sequences for a recursive-filter so as to decrease the computation cycle of the recursive-filter. Therefore, the time complexity of the RDFT can be minimized, namely, increasing the throughput of the RDFT.

Abstract: An electrical stimulation apparatus and an electrical stimulation method are provided. The electrical stimulation apparatus may include an electrode unit, a measurement unit and a stimulation unit. The electrode unit is used for contacting a tissue of interest (target tissue). The measurement unit is coupled to the electrode unit. The measurement unit measure a tissue characteristic of the target tissue. The stimulation unit is coupled to the measurement unit and the electrode unit. The stimulation unit stimulates the target tissue through the electrode unit by using an electrical stimulation signal, and the stimulation unit determines an amount of charge of the electrical stimulation signal according to the tissue characteristic measured by the measurement unit.

Abstract: A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position Vf of the PMOS transistor circuit having its output Vg, with its purpose of keeping Vg?Vf at a constant value. The PMOS transistor circuit may produce body effect through various different bulk voltages. Through the auto-tuning circuit, Vg and Vf are kept constant to make current of transistor to produce compensation effect, such that regardless of Va>Vb or Va<Vb, a large resistance is maintained. Through utilizing the tunable voltage-controlled pseudo-resistor structure, constant resistance can be maintained under high input voltage, hereby reducing drifting of common-mode voltage, in achieving a superior resistance effect.

Abstract: A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position Vf of the PMOS transistor circuit having its output Vg, with its purpose of keeping Vg?Vf at a constant value. The PMOS transistor circuit may produce body effect through various different bulk voltages. Through the auto-tuning circuit, Vg and Vf are kept constant to make current of transistor to produce compensation effect, such that regardless of Va>Vb or Va<Vb, a large resistance is maintained. Through utilizing the tunable voltage-controlled pseudo-resistor structure, constant resistance can be maintained under high input voltage, hereby reducing drifting of common-mode voltage, in achieving a superior resistance effect.

Abstract: A joint carrier synchronization and channel equalization method for OFDM systems, that is suitable for use in a receiver of said orthogonal frequency division multiplexer (OFDM) systems, comprising the following steps: firstly, receiving a reception signal sample of an OFDM symbol, and obtaining simultaneously a phase error and a gain error on each sub-channel in a frequency domain, through outputting a sub-channel signal on each said sub-channel in said frequency domain; next, obtaining an execution carrier frequency offset factor, an execution phase compensation factor, and an execution gain compensation factor based on said phase error and said gain error; and finally, eliminating a phase offset of said reception signal sample of a next symbol in a time domain based on said factors, and compensating a magnitude distortion and a phase distortion on each said sub-channel in said frequency domain for said reception signal of said next symbol.

Abstract: A DHT-based OFDM transmitter and receiver use discrete Hartley transform to implement multicarrier transmission. A transmission terminal (or a receiving terminal) of a transmitter and receiver comprises two IDHT (or DHT) processors and a diagonal processing device. The two IDHT processors make the DHT-OFDM system transmit the 2D modulation signal to increase the bandwidth efficiency. The diagonal processing device is used to diagonalize the circulant channel matrix into discrete memoryless subchannels, and thus only one-tap frequency domain equalizer can compensate the channel effects. Besides, the proposed DHT-OFDM transmitter and receiver are also compatible with a conventional DFT-OFDM system, and they can flexibly works with the conventional DFT-OFDM transmitter and receiver.

Abstract: A SRAM architecture includes a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.

Abstract: A low complexity and low power phase shift keying demodulator structure includes a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler. The digitizer digitizes a BPSK signal for an output waveform. The phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal. The binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor. The sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only a small capacitance.

Abstract: A SRAM architecture comprises a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out stored in. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.

Abstract: A joint carrier synchronization and channel equalization method for OFDM systems, that is suitable for use in a receiver of said orthogonal frequency division multiplexer (OFDM) systems, comprising the following steps: firstly, receiving a reception signal sample of an OFDM symbol, and obtaining simultaneously a phase error and a gain error on each sub-channel in a frequency domain, through outputting a sub-channel signal on each said sub-channel in said frequency domain; next, obtaining an execution carrier frequency offset factor, an execution phase compensation factor, and an execution gain compensation factor based on said phase error and said gain error; and finally, eliminating a phase offset of said reception signal sample of a next symbol in a time domain based on said factors, and compensating a magnitude distortion and a phase distortion on each said sub-channel in said frequency domain for said reception signal of said next symbol.

Abstract: A low complexity and low power phase shift keying demodulator structure comprises: a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler; wherein the digitizer digitizes a BPSK signal for an output waveform, the phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal, the binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor, the sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only small capacitance.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

Abstract: An amplitude shift keying (ASK) demodulation circuit based on a self sample as a basis application in an organism implantation microsystem is a low-cost and high-performance ASK demodulation core, comprising a pulse shaper, a voltage scaler, a level contrastor, and a self-sampler for achievement of the demodulation core provided pretty digital features, and needs no passive resistor and capacitor, which may reduce the cost of design and prevent the problem with precision. Further, in the aspect of active point, the size of a transistor may be adjusted for variable control, and hence levels determined among modulation signals may be reduced to lower the complexity of voltage regulator in design.

Abstract: An efficient method for calculating the step-sizes for a frequency-domain equalizer of a discrete-multitone communications system using signal power estimation and tone grouping (SPE-TG) while on-line. The SPE-TG method is used to calculate a plurality of subchannel step-sizes which are then stored in a lookup table. When on-line, the method uses signal power estimation to select step sizes for each tone, and uses these step sizes for frequency domain equalization. The SPE-TG method simplifies the calculations necessary for frequency domain equalization, thereby saving significant hardware and/or processing resources. The SPE-TG method is reliable and robust, and does not depend upon assumptions about the line, location, or channel.

Abstract: A discrete multi-tone (DMT) communication system is provided herein, replacing the conventional inversed discrete Fourier transform (IDFT) and DFT with IDHT (together with the complex-to-real transformation) and a DHT alone respectively at the transmitting end and the receiving end. A DHT-based frequency-domain equalizer (FEQ) at the receiving end equalizes each of the 0-th to (N?1)-th DHT subchannels, where N is the number of point of the DHT. Finally, each of the 0-th to ( N 2 - 1 ) - th subchannels of the DMT system is obtained by combining the k-th and (N-k)-th subchannels of the DHT-based FEQ for k=0, 1, . . . , ( N 2 - 1 ) .

Abstract: A method of designing a multi-channel micro-electrical stimulation structure with an equivalent current source that works with an adiabatic baseband based on direct-carrier energy extraction matches with a baseband circuitry designed for energy recovery with the equivalent current source. A controllable pulse width modulation signal at the operating rate near to the carrier rate is used to implement the charge accumulation for the stimulation resolution on the time sequence axis. The design of equivalent current source may reduce the defects caused by a general D/A converter for full-scale stimulation resolution. Further, the adiabatic design is applied, so the redundant power consumption caused at the higher clock rate is minimized and, due to the switching current in the baseband circuitry significantly decreasing, only one voltage regulator circuit is required for the operation of analog and digital circuits that is imbedded into a chip, thereby more design cost being reduced.

Abstract: An amplitude shift keying (ASK) demodulation circuit based on a self sample as a basis application in an organism implantation microsystem is a low-cost and high-performance ASK demodulation core, comprising a pulse shaper, a voltage scaler, a level contrastor, and a self-sampler for achievement of the demodulation core provided pretty digital features, and needs no passive resistor and capacitor, which may reduce the cost of design and prevent the problem with precision. Further, in the aspect of active point, the size of a transistor may be adjusted for variable control, and hence levels determined among modulation signals may be reduced to lower the complexity of voltage regulator in design.

Abstract: A discrete multi-tone (DMT) communication system is provided herein, replacing the conventional inversed discrete Fourier transform (IDFT) and DFT with IDHT (together with the complex-to-real transformation) and a DHT alone respectively at the transmitting end and the receiving end. A DHT-based frequency-domain equalizer (FEQ) at the receiving end equalizes each of the 0-th to (N?1)-th DHT subchannels, where N is the number of point of the DHT. Finally, each of the 0-th to (N/2?1)-th subchannels of the DMT system is obtained by combining the k-th and (N-k)-th subchannels of the DHT-based FEQ for k=0, 1, . . . , (N/2?1).