Abstract: The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

Abstract: A method, apparatus, and system permits an access terminal (“AT”) for a multi-carrier CDMA wireless communication system to concurrently receive data on N different-frequency carriers while restricting one or more parameters that affect data reception rate, so that limited resources of the AT will be sufficient to properly process data packets on the N carriers. The data rate controlling parameter may be “I,” the number of supported H-ARQ channels for one or more of the N carriers. A relationship may be defined between the number of supported forward and/or reverse link carriers, versus the number of supported H-ARQ channels and/or other data rate controlling parameters. Messages may enable identification of AT characteristics, and configuration and/or dynamic re-configuration of AT data communication capabilities that are related to different values of N and corresponding different data rate controlling parameters.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

Abstract: The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

Abstract: Prefetching data to a low level memory of a computer system is accomplished utilizing an instruction location indicator related to an upcoming instruction to identify a next data prefetch indicator and then utilizing the next data prefetch indicator to locate the corresponding prefetch data within the memory of the computer system. The prefetch data is located so that the prefetch data can be transferred to a primary cache where the data can be quickly fetched by a processor when the upcoming instruction is executed. The next data prefetch indicator is generated by carrying out the addressing mode function that is embedded in an instruction only when the addressing mode of the instruction is a deterministic addressing mode such as a sequential.

Abstract: A data processing system and method for arranging and accessing information that crosses cache lines utilize dual cache columns. The dual cache columns are formed of two access-related cache lines. The two cache columns contain sequential information that is stored in cache lines in a sequential and alternating format. A processor makes a request for a particular instruction. An instruction fetch unit takes the instruction request and creates a second instruction request in addition to the first instruction request. The two instruction requests are sent simultaneously to first and second content addressable memories (CAMs) respectively associated with the first and second cache columns. The CAMs are simultaneously searched and any cache hits are forwarded to a switch. The switch combines the relevant portions of the two cache lines and delivers the desired instruction to a processor. A method of accessing and distributing stored data in a computer system is also described.

Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

Abstract: An apparatus and method are disclosed for activating a memory location within a memory device. In an apparatus aspect of the invention, a memory device is disclosed. The memory device includes an enable unit arranged to receive a plurality of address signals and a clock signal and to output an activation signal. The address signals has an associated worst case delay, and the enable unit is further arranged to generate an enable signal that is delayed from the clock signal by at least about the worst case delay. The memory device further includes a memory array arranged to receive the activation signal in response to which a corresponding memory location is activated.

Abstract: A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers.

Abstract: A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary of the load instruction and a real address to a word boundary of the executing store instruction match, and identifying a bypass error condition for the load instruction when the load instruction has executed out-of-order with respect to the executing store instruction. In a system aspect, the system includes a load queue, detection logic, and completion logic. The load queue includes a real page number buffer for storing a real address to a word boundary for each executed load instruction. The detection logic compares real addresses to a word boundary for a load instruction against an executing store instruction and compares a program order of the load instruction and the executing store instruction when the real addresses to a word boundary match.

Abstract: A method and apparatus for executing instructions within a processor which completes instructions according to a program order are disclosed. The processor has multiple rename buffers for temporarily storing results of instructions, a number of registers, and an execution unit. The execution unit has a reservation data structure comprising a plurality of entries for storing instructions to be executed by the execution unit and a single operand buffer for storing one or more operands of a single instruction. According to the present invention, an instruction is received at the execution unit. The instruction is then stored within the reservation data structure within the execution unit in association with information specifying a source of an operand of the instruction. Sources of operands of instructions include the rename buffers and the registers. A determination is then made if the instruction is a next instruction to be executed by the execution unit.