Abstract: An apparatus includes a high side switch connected between an input voltage bus and a load terminal, the load terminal being configured to be coupled to a load, a high side gate drive circuit configured to generate a gate drive signal for the high side switch, and a resonance suppression circuit having a first terminal connected to a gate of the high side switch, and a second terminal connected to the load terminal, wherein after a predetermined delay counting from a falling edge of an enable signal applied to the high side gate drive circuit, the resonance suppression circuit is configured to be active, and after a voltage on the load terminal rises above a ground voltage potential for a first time, the resonance suppression circuit is configured to pull a voltage on the gate of the high side switch down to a low voltage.

Abstract: A computing device includes last level cache (LLC) for processing cores and a separate input/output (I/O) LLC for use in facilitating data transfers between the computing device and one or more I/O devices. The I/O LLC is configured to include a set of partitions corresponding to a set of classes. Usage of the partitions in the set of partitions is monitored and the set of partitions is dynamically adjusted based on the usage. A process in a particular one of the classes makes a data request and a particular one of the partitions associated with the particular class is used in the data request.

Abstract: A grounding system includes a first circuit portion and a second circuit portion. The first circuit portion is connected to an input voltage bus and has a terminal being a first ground. The second circuit portion is connected between the first ground and a second ground, and includes a switch branch and a resistor branch. When the positive terminal of a power supply is connected to the input voltage bus and the negative terminal of the power supply is connected to the second ground, the switch branch establishes a first current path between the first ground and the second ground and shorts a first diode in the switch branch. When the positive terminal is connected to the second ground and the negative terminal is connected to the input voltage bus, the switch branch disconnects the first current path and stops shorting the first diode.

Abstract: A platform-independent method of securely resetting a processing device includes detecting a predefined trigger event by a baseboard management controller (BMC) that executes system firmware on behalf of a managed host. In response to the predefined trigger event, the system is booted into a safe mode. While in the safe mode, a central processing system of the managed host is maintained in an off state, and a self-heal agent detects architectural characteristics of the managed host, establishes a connection to a cloud-based firmware catalog service, transmits the architectural characteristics of the managed host to the cloud-based firmware catalog service, and downloads a new version of system firmware from the cloud-based firmware catalog service that is compatible with the architectural characteristics of the managed host. The new version of the system firmware is automatically installed without powering on the central processing system of the managed host.

Abstract: Disclosed herein is a system for limiting the rate at which system management interrupts can suspend normal execution of a central processing unit (CPU) by switching the operating mode of the CPU from one of the real mode or the protected mode to the system management mode. The rate limits imposed by the system provides a protective layer against cyberattacks (e.g., a distributed denial-of-service (DDoS) attack) from malicious actors and ensures the CPU can be more efficient regarding the execution of workloads (e.g., processing threads).

Abstract: Diagnostic instruments and methods of operating diagnostic instruments are provided. Methods of operating a diagnostic instrument includes providing the diagnostic instrument having one or more modules, wherein the one or more modules are configured to analyze specimens; providing a specimen sorter coupled to the diagnostic instrument; and sorting specimens into at least first group and a second group, wherein specimens in the first group are to be analyzed by at least one of the one or more modules, and specimens in the second group are not to be analyzed by any of the one or more modules. Other sorting methods and diagnostic instruments are provided.

Abstract: A number of slots in a chassis of an information handling system and a number of a plurality of sleds to be housed in the chassis may be determined. An airflow for each of the plurality of sleds in each of the plurality of placement configurations may be determined based, at least in part, on the number of slots in the chassis and the number of the plurality of sleds to be housed in the chassis. A recommended placement for each of the sleds may be determined based at least in part on the airflow for each of the plurality of sleds for the plurality of placement configurations. A notification may be generated comprising the recommended placements for each of the plurality of sleds.

Abstract: A system for dispensing a beverage into a cup. Dispensing hardware is configured to dispense the beverage into the cup. A vision system captures an image of the cup within a dispensing area of the system. A model contains data corresponding to the cup being full. A control system compares the image of the cup to the model and controls the dispensing hardware to dispense the beverage into the cup based on the comparison of the image of the cup to the model.

Abstract: The present disclosure describes techniques for training a neural network such that the trained network can be implemented to perform a utility task (e.g., a classification task) while inhibiting performance of a secondary task (e.g., a privacy-violating task). In some embodiments, the techniques include training a neural network using a first loss associated with a first task and a second loss associated with a second task different from the first task. In some embodiments, this includes performing a first training operation associated with the first loss, and performing a second training operation associated with the second loss, wherein the second training operation includes providing, to the neural network, a plurality of input items associated with the second task.

Abstract: A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

Abstract: A number of slots in a chassis of an information handling system and a number of a plurality of sleds to be housed in the chassis may be determined. An airflow for each of the plurality of sleds in each of the plurality of placement configurations may be determined based, at least in part, on the number of slots in the chassis and the number of the plurality of sleds to be housed in the chassis. A recommended placement for each of the sleds may be determined based at least in part on the airflow for each of the plurality of sleds for the plurality of placement configurations. A notification may be generated comprising the recommended placements for each of the plurality of sleds.

Abstract: A quality control method for a diagnostic analyzer includes performing a quality control test or a plurality of specimen tests; determining, with a controller, that a result of the quality control test or a plurality of specimen test results is outside of a threshold; monitoring one or more mechanical devices of the diagnostic analyzer with the controller; receiving, by the controller, an error code indicating an error in a mechanical device of the one or more mechanical devices; and initiating a calibration procedure in response to the result of the quality control test or the plurality of specimen test results being outside of the threshold and receiving the error code. Other apparatus and methods are disclosed.

Abstract: A method of analyzing a specimen includes detecting a specimen integrity error in the specimen; capturing an image of the specimen; sending the image of the specimen to a customer support center at a remote location; analyzing the image of the specimen at the customer support center; and determining a cause of the specimen integrity error in response to analyzing the image of the specimen. Diagnostic analyzers and diagnostic systems are also disclosed.

Abstract: Various implementations disclosed herein include devices, systems, and methods that involve federated learning techniques that utilize locally-determined ground truth data that may be used in addition to, or in the alternative to, user-provided ground truth data. Some implementations provide an improved federated learning technique that creates ground truth data on the user device using a second prediction technique that differs from a first prediction technique/model that is being trained. The second prediction technique may be better but may be less suited for real time, general use than the first prediction technique.

Abstract: A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

Abstract: A system for dispensing a beverage into a cup. Dispensing hardware is configured to dispense the beverage into the cup. A vision system captures an image of the cup within a dispensing area of the system. A model contains data corresponding to the cup being full. A control system compares the image of the cup to the model and controls the dispensing hardware to dispense the beverage into the cup based on the comparison of the image of the cup to the model.

Abstract: A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

Abstract: The omnidirectional ultra-wideband antenna is a variant on a monocone antenna, particularly including a supplemental radiating element. The omnidirectional ultra-wideband antenna includes an electrically conductive conical surface having a vertex end and a base end, and a supplemental radiating element having a first portion and a second portion. The first portion extends from the base end of the electrically conductive conical surface, the first portion being positioned between the base end of the electrically conductive conical surface and the second portion. The vertex end of the electrically conductive conical surface is positioned adjacent to, and spaced apart from, a first surface of a ground plane plate. At least one electrically conductive rod is provided, a first end of the rod being secured to the second portion, and a second end of each rod being mounted on the first surface of the ground plane plate.

Abstract: The omnidirectional multiband antenna is a variant on a monocone antenna, particularly including a corrugated extending surface for lowering the low frequency cutoff of the monocone antenna. The omnidirectional multiband antenna includes an electrically conductive conical surface, having a vertex end and a base end, and at least one electrically conductive annular member mounted on the base end. The at least one electrically conductive annular member is formed from a plurality of stacked segments and has a corrugated exterior surface. The vertex end of the electrically conductive conical surface is positioned adjacent to, and spaced apart from, a first surface of a ground plane plate. A plurality of cylindrical rods is provided, a first end of each rod being secured to the at least one electrically conductive annular member, and a second end of each rod being mounted on the first surface of the ground plane plate.

Abstract: A processor device includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution, The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register flies includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.