Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: This disclosure is directed to a machine-based patient-specific seizure classification system. In general, an example system may comprise a non-linear SVM seizure classification system-on-chip (SoC) with multichannel EEG data acquisition and storage for epileptic patients is presented. The SoC may integrate a hardware-efficient log-linear Gaussian Basis Function engine, floating point piecewise linear natural log, and low-noise, high dynamic range readout circuits. In at least one example implementation, the SoC may consume 1.83 ?J/classification while classifying 8 channel results with an average detection rate, average false alarm rate and latency of 95.1%, 0.94% and <2 s, respectively.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: This disclosure is directed to a machine-based patient-specific seizure classification system. In general, an example system may comprise a non-linear SVM seizure classification system-on-chip (SoC) with multichannel EEG data acquisition and storage for epileptic patients is presented. The SoC may integrate a hardware-efficient log-linear Gaussian Basis Function engine, floating point piecewise linear natural log, and low-noise, high dynamic range readout circuits. In at least one example implementation, the SoC may consume 1.83W/classification while classifying 8 channel results with an average detection rate, average false alarm rate and latency of 95.1%, 0.94% and <2 s, respectively.