Patents by Inventor MUHAMMAD AZIM BIN SYED SULAIMAN

MUHAMMAD AZIM BIN SYED SULAIMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus for controlling warpage in wafer level packaging processes
    Patent number: 11421316
    Abstract: Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 ?m l/s fine pitch patterning.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 23, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prayudi Lianto, Mohamed Rafi, Muhammad Azim Bin Syed Sulaiman, Guan Huei See, Ang Yu Xin Kristy, Karthik Elumalai, Sriskantharajah Thirunavukarasu, Arvind Sundarrajan
  • METHODS AND APPARATUS FOR CONTROLLING WARPAGE IN WAFER LEVEL PACKAGING PROCESSES
    Publication number: 20200131624
    Abstract: Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 ?m l/s fine pitch patterning.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: PRAYUDI LIANTO, MOHAMED RAFI, MUHAMMAD AZIM BIN SYED SULAIMAN, GUAN HUEI SEE, ANG YU XIN KRISTY, KARTHIK ELUMALAI, SRISKANTHARAJAH THIRUNAVUKARASU, ARVIND SUNDARRAJAN