Patents by Inventor Muhammad E. S. Elrabaa

Muhammad E. S. Elrabaa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200241899
    Abstract: An FPGA virtualization platform including a network controller configured to provide an interface to an external network; a static logic section coupled to the network controller, and one or more reconfigurable regions each having a virtualized field programmable gate array vFPGA) that includes a wrapper and a user design.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Amran A. AL-AGHBARI, Muhammad E.S. ELRABAA
  • Patent number: 9188627
    Abstract: The digital integrated circuit testing and characterization system and method provides high-speed testing for digital IC prototypes. A stand-alone circuit, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), implements a test and characterization processor (TACP). Supporting test circuitry is fabricated on board a prototyping chip to facilitate the test and characterization process. Test procedures and data may be downloaded to the TACP memory through a computer via a standard interface. The TACP administers the user-specified test procedures to one of several possible circuits on the prototyping chip. Test results are stored and collected via the on-board support test circuitry in communication with the TACP.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: November 17, 2015
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventor: Muhammad E. S. Elrabaa
  • Publication number: 20150122560
    Abstract: The multi-car trackless transportation system includes a pilot car and at least one secondary car connected to one another in a manner similar to a conventional tram system or the like. Each of the cars is connected to adjacent cars by pivotal connectors. The pilot car and the at least one secondary car each include an individual motor, drive system and steering system. In order to develop a virtual tramway or path, the pilot car transmits instantaneous velocity and steering angles measurements to the secondary car. The secondary car then applies these signals so that it has an equivalent velocity and steering angle at the same location as the pilot car when the measurements were taken.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: King Fahd University Of Petroleum And Minerals
    Inventor: MUHAMMAD E.S. ELRABAA
  • Patent number: 8610511
    Abstract: The high-frequency digitally controlled oscillator includes fully digital cells capable of being ported to any CMOS fabrication process. The oscillator has a basic modular architecture comprising a digitally controlled digital ring oscillator (DRO) having a plurality of delay stages, a counter divider and a selection multiplexer. The DRO generates the basic (intrinsic) high frequency range and the counter provides the remaining ranges through division by multiples of two. The multiplexer provides a selection mechanism for the required range of frequencies. Load capacitances to the delay stages are added/removed to control delay via utilization of a unique capacitive cell driven synchronously by two ring oscillators such that the capacitance could be added or removed utilizing the Miller effect. Moreover, multiple capacitive load cells can be added to the same stage.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 17, 2013
    Assignees: King Fahd University of Petroleum and Minerals, King Abdulaziz City for Science and Technology
    Inventor: Muhammad E. S. Elrabaa
  • Publication number: 20130116961
    Abstract: The digital integrated circuit testing and characterization system and method provides high-speed testing for digital IC prototypes. A stand-alone circuit, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), implements a test and characterization processor (TACP). Supporting test circuitry is fabricated on board a prototyping chip to facilitate the test and characterization process. Test procedures and data may be downloaded to the TACP memory through a computer via a standard interface. The TACP administers the user-specified test procedures to one of several possible circuits on the prototyping chip. Test results are stored and collected via the on-board support test circuitry in communication with the TACP.
    Type: Application
    Filed: May 14, 2012
    Publication date: May 9, 2013
    Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventor: MUHAMMAD E.S. ELRABAA
  • Patent number: 8351489
    Abstract: A two-phase return-to-zero asynchronous transceiver is provided. The two-phase return-to-zero asynchronous transceiver is designed for on-chip interconnects. The transceiver includes a multi-stage transceiver arranged in a dual rail configuration, along with a weak keeper for each stage, a data driver for each stage, and an enable control circuit for selectively enabling the data driver, such that the data driver outputs data to a subsequent stage of the multi-stage transceiver. The enable control circuit further utilizes a handshaking protocol, which may be implemented at 0.13 ?m and 1.2 Volts. The transceiver circuit achieves a throughput of approximately 3 Gb/s with wire lengths of approximately 100 ?m.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: January 8, 2013
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Muhammad E. S. Elrabaa
  • Patent number: 8352774
    Abstract: The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 8, 2013
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Muhammad E. S. Elrabaa
  • Publication number: 20110320854
    Abstract: The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Inventor: Muhammad E.S. Elrabaa
  • Publication number: 20100309961
    Abstract: The two-phase return-to-zero asynchronous transceiver is delay-insensitive and specifically designed for on-chip interconnects. A handshaking protocol utilizes a return-to-zero data format, thereby simplifying communication circuits' design significantly. The robust transceiver circuits utilizing the handshaking protocol can be implemented at 0.13 ?m and 1.2 Volts.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Inventor: Muhammad E.S. Elrabaa