Patents by Inventor Muhammad Kalimuddin Khan
Muhammad Kalimuddin Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10129011Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.Type: GrantFiled: May 25, 2017Date of Patent: November 13, 2018Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney, Philip P. E. Quinlan, Shane O'Mahony
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Publication number: 20170264422Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Inventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney, Philip P.E. Quinlan, Shane O'Mahony
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Patent number: 9749125Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.Type: GrantFiled: December 12, 2014Date of Patent: August 29, 2017Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney
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Patent number: 9673962Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.Type: GrantFiled: February 17, 2016Date of Patent: June 6, 2017Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney, Philip P. E. Quinlan, Shane O'Mahony
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Patent number: 9594100Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.Type: GrantFiled: September 6, 2013Date of Patent: March 14, 2017Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney, Michael Deeney, Niall Kevin Kearney
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Patent number: 9553717Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.Type: GrantFiled: March 18, 2014Date of Patent: January 24, 2017Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Philip Quinlan, Kenneth J. Mulvaney
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Patent number: 9391578Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.Type: GrantFiled: June 11, 2014Date of Patent: July 12, 2016Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Michael J. Deeney, Niall Kevin Kearney, Kenneth J. Mulvaney, Shane A. O'Mahony
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Publication number: 20160173272Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney
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Patent number: 9246669Abstract: Apparatus and method for acquiring and tracking a data signal are disclosed. Two different CDR circuits are configured to acquire and track data based on two different modulation schemes. While in the acquisition mode, the first CDR circuit may acquire data signal by sampling the signal at a reduced clock rate and handover to the second CDR circuit when a preamble is found. Also in the acquisition mode, the data acquisition and tracking circuit may determine the power level of the preamble signal and dynamically adjust the threshold level for the tracking period upon finding of the preamble.Type: GrantFiled: May 22, 2014Date of Patent: January 26, 2016Assignee: Analog Devices GlobalInventors: Muhammad Kalimuddin Khan, Philip E. Quinlan, Kenneth J. Mulvaney
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Publication number: 20150365118Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.Type: ApplicationFiled: June 11, 2014Publication date: December 17, 2015Inventors: Muhammad Kalimuddin Khan, Michael J. Deeney, Niall Kevin Kearney, Kenneth J. Mulvaney, Shane A. O'Mahony
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Publication number: 20150341161Abstract: Apparatus and method for acquiring and tracking a data signal are disclosed. Two different CDR circuits are configured to acquire and track data based on two different modulation schemes. While in the acquisition mode, the first CDR circuit may acquire data signal by sampling the signal at a reduced clock rate and handover to the second CDR circuit when a preamble is found. Also in the acquisition mode, the data acquisition and tracking circuit may determine the power level of the preamble signal and dynamically adjust the threshold level for the tracking period upon finding of the preamble.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Inventors: Muhammad Kalimuddin Khan, Philip E. Quinlan, Kenneth J. Mulvaney
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Publication number: 20150270948Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Inventors: Muhammad Kalimuddin Khan, Philip Quinlan, Kenneth J. Mulvaney
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Publication number: 20150073739Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: Analog Devices TechnologyInventors: Muhammad Kalimuddin Khan, Kenneth J. Mulvaney, Michale Deeney, Niall Kevin Kearney