Patents by Inventor Muhammad M. Khellah

Muhammad M. Khellah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043251
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 11, 2021
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Patent number: 10892012
    Abstract: An apparatus, vision processing unit, and method are provided for clustering motion events in a content addressable memory. A motion event is received including coordinates in an image frame that have experienced a change and a timestamp of the change. A determination is made as to whether determine whether there is a valid entry in the memory having coordinates within a predefined range of coordinates included in the motion event. In response to a determination that there is the valid entry having the coordinates within the predefined range of coordinates included in the motion event, write to the valid entry the coordinates and the timestamp in the motion event.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Turbo Majumder, Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Patent number: 10878313
    Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 29, 2020
    Assignee: INTEL CORPORATION
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Publication number: 20200393861
    Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah
  • Patent number: 10755771
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Patent number: 10748060
    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Publication number: 20200258890
    Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Charles AUGUSTINE, Somnath PAUL, Muhammad M. KHELLAH, Chen KOREN
  • Patent number: 10707877
    Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Turbo Majumder, Minki Cho, Carlos Tokunaga, Praveen Mosalikanti, Nasser A. Kurd, Muhammad M. Khellah
  • Patent number: 10698432
    Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah
  • Patent number: 10685688
    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah
  • Publication number: 20200183922
    Abstract: An apparatus is described. The apparatus includes a nearest neighbor search circuit to perform a search according to a first stage search and a second stage search. The nearest neighbor search circuit includes a first stage circuit and a second stage circuit. The first stage search circuit includes a hash logic circuit and a content addressable memory. The hash logic circuit is to generate a hash word from a input query vector. The hash word has B bands. The content addressable memory is to store hashes of a random access memory's data items. The hashes each have B bands. The content addressable memory is to compare the hashes against the hash word on a sequential band-by-band basis. The second stage circuit char the random access memory and a compare and sort circuit. The compare and sort circuit is to receive the input query vector. The random access memory has crosswise bit lines coupled to the compare and sort circuit.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Inventors: Wootaek LIM, Minchang CHO, Somnath PAUL, Charles AUGUSTINE, Suyoung BANG, Turbo MAJUMDER, Muhammad M. KHELLAH
  • Publication number: 20200133884
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a memory side cache and an NVRAM system memory. The memory controller has logic circuitry to favor items cached in the memory side cache that are expected to be written to above items cached in the memory side cache that are expected to only be read from.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 30, 2020
    Inventors: Zeshan A. CHISHTI, Somnath PAUL, Charles AUGUSTINE, Muhammad M. KHELLAH
  • Patent number: 10635968
    Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah, Sadique Ul Ameen Sheik
  • Patent number: 10528473
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Patent number: 10511224
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 10489702
    Abstract: Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight memory.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Patent number: 10423203
    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Rafael Rios, Somnath Paul, Muhammad M. Khellah
  • Patent number: 10418076
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
  • Patent number: 10410699
    Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Bhushan Borole, Muhammad M. Khellah, Pascal A. Meinerzhagen
  • Patent number: 10359834
    Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Muhammad M. Khellah, James W. Tschanz