Abstract: An improved method and system for the determination of jitter buffers enables the generation of buffers having sizes and delays such that, as designed, the buffers capture a substantial majority of packets while not being resource intensive. The present methods and systems provide for improved jitter buffer management by deriving playout buffer adjustments from a plurality of variances, centered around a distribution peak, or mean average delay. The playout buffer monitor uses the buffer adjustments, in size and delay, to select, store and playout packets at their adjusted playout time. The present invention may be employed in a media gateway that enables data communications among heterogenous networks and may be specifically deployed to manage jitter experienced in the course of receiving packetized data and processing the data for further transmission through a packet-based or circuit-switched network.

Abstract: An improved method and system for the determination of jitter buffers enables the generation of buffers having sizes and delays such that, as designed, the buffers capture a substantial majority of packets while not being resource intensive. The present methods and systems provide for improved jitter buffer management by deriving playout buffer adjustments from a plurality of variances, centered around a distribution peak, or mean average delay. The playout buffer monitor uses the buffer adjustments, in size and delay, to select, store and playout packets at their adjusted playout time. The present invention may be employed in a media gateway that enables data communications among heterogenous networks and may be specifically deployed to manage jitter experienced in the course of receiving packetized data and processing the data for further transmission through a packet-based or circuit-switched network.

Abstract: An improved method and system for the determination of jitter buffers enables the generation of buffers having sizes and delays such that, as designed, the buffers capture a substantial majority of packets while not being resource intensive. The present methods and systems provide for improved jitter buffer management by deriving playout buffer adjustments from a plurality of variances, centered around a distribution peak, or mean average delay. The playout buffer monitor uses the buffer adjustments, in size and delay, to select, store and playout packets at their adjusted playout time. The present invention may be employed in a media gateway that enables data communications among heterogenous networks and may be specifically deployed to manage jitter experienced in the course of receiving packetized data and processing the data for further transmission through a packet-based or circuit-switched network.

Abstract: The present invention is a system on chip having a scalable, distributed processing architecture and memory capabilities through a plurality of parallel processing layers. In one embodiment, the processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (Pus), specially designed for conducting a defined set of processing tasks, are in communication with program memories and data memories.

Abstract: An improved method and system for the determination of jitter buffers enables the generation of buffers having sizes and delays such that, as designed, the buffers capture a substantial majority of packets while not being resource intensive. The present methods and systems provide for improved jitter buffer management by deriving playout buffer adjustments from a plurality of variances, centered around a distribution peak, or mean average delay. The playout buffer monitor uses the buffer adjustments, in size and delay, to select, store and playout packets at their adjusted playout time. The present invention may be employed in a media gateway that enables data communications among heterogenous networks and may be specifically deployed to manage jitter experienced in the course of receiving packetized data and processing the data for further transmission through a packet-based or circuit-switched network.

Abstract: The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks.