Abstract: An I/O (input/output) bus arbiter to be used in conjunction with a compatible CPU (processor) to effect burst mode data transfers in all I/O accesses that remove the need for DMA (Direct-Memory-Access) signals, Bus-request/Bus-grant signals, and bridges consequently removing the need for a bus system to connect peripherals such as the PCI (Peripheral-Connect-Interface). The I/O arbiter consists of an interrupt controller with circular buffers, FIFOs (First-In-First-Out) and port engines for directly attaching devices with proper interface buffers, together with a compatible CPU interrupt signals, and synchronous data transfers with only this one arbiter.

Abstract: A model and access method for devices to be homogenous irrespective whether they be character or block types. The access method is closely coupled between a host processor and the input/output (I/O) ports either through the data ports to the FIFOs (First-In-First-Out), or the control ports of the devices. Data transfers to the devices are effected through their data ports, while the control words in the form of bytecodes are sent through the control ports. The access method enables parallel processing within independent devices as they can execute device specific codes in parallel with the system software or kernel. The bytecodes are portable across hardware platforms since they serve as command words for configuration of devices and command instructions for the burst mode transfer of data between devices and a processor.

Abstract: A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer. The Input-Output (I/O) is uniformly viewed and treated as an individual First-In-First-Out (FIFO) device. Pluralities of memory areas are implemented for user stack, kernel stack, interrupt stack and procedure call stack. Only one I/O arbiter is necessary for a CPU model that arbitrates between a plurality of FIFOs substituting data caches for on-chip implementation, thus eliminating traditional data transfer techniques using Direct-Memory-Access (DMA), bus control and lock signals leaving just the interrupt signals and the new synchronous signals for an easy and streamlined system design and CPU model. Supporting an interrupt-driven, FIFO-based I/O and synchronous burst data transfer the CPU employs a simple linear large register sets without bank switching.

Abstract: An I/O (input/output) bus arbiter to be used in conjunction with a compatible CPU (processor) to effect burst mode data transfers in all I/O accesses that remove the need for DMA (Direct-Memory-Access) signals, Bus-request/Bus-grant signals, and bridges consequently removing the need for a bus system to connect peripherals such as the PCI (Peripheral-Connect-Interface). The I/O arbiter consists of an interrupt controller with circular buffers, FIFOs (First-In-First-Out) and port engines for directly attaching devices with proper interface buffers, together with a compatible CPU interrupt signals, and synchronous data transfers with only this one arbiter.

Abstract: A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer. The Input-Output (I/O) is uniformly viewed and treated as an individual First-In-First-Out (FIFO) device. Pluralities of memory areas are implemented for user stack, kernel stack, interrupt stack and procedure call stack. Only one I/O arbiter is necessary for a CPU model that arbitrates between a plurality of FIFOs substituting data caches for on-chip implementation, thus eliminating traditional data transfer techniques using Direct-Memory-Access (DMA), bus control and lock signals leaving just the interrupt signals and the new synchronous signals for an easy and streamlined system design and CPU model. Supporting an interrupt-driven, FIFO-based I/O and synchronous burst data transfer the CPU employs a simple linear large register sets without bank switching.

Abstract: A model and access method for devices to be homogenous irrespective whether they be character or block types. The access method is closely coupled between a host processor and the input/output (I/O) ports either through the data ports to the FIFOs (First-In-First-Out), or the control ports of the devices. Data transfers to the devices are effected through their data ports, whilst the control words in the form of bytecodes are sent through the control ports. The access method enables parallel processing within independent devices as they can execute device specific codes in parallel with the system software or kernel. The bytecodes are portable across hardware platforms since they serve as command words for configuration of devices and command instructions for the burst mode transfer of data between devices and a processor.