Patents by Inventor Muhammad Nummer
Muhammad Nummer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10177751Abstract: A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.Type: GrantFiled: January 30, 2017Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Muhammad Nummer
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Publication number: 20170346467Abstract: A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.Type: ApplicationFiled: January 30, 2017Publication date: November 30, 2017Inventor: Muhammad NUMMER
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Patent number: 9716507Abstract: A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.Type: GrantFiled: April 14, 2016Date of Patent: July 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Muhammad Nummer, Rob Abbott
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Patent number: 8754685Abstract: A circuit includes a delay line and a delay locked loop. The circuit is configured to receive a delay parameter and a clock signal. The delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop. The delay locked loop is configured to determine a difference between the frequency of the clock signal and the frequency of the oscillator based on a phase of an output of the oscillator and a phase of the clock signal after the output of the oscillator and the clock signal are aligned. The delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter.Type: GrantFiled: November 28, 2012Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Muhammad Nummer, Dirk Pfaff
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Publication number: 20140145771Abstract: A circuit includes a delay line and a delay locked loop. The circuit is configured to receive a delay parameter and a clock signal. The delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop. The delay locked loop is configured to determine a difference between the frequency of the clock signal and the frequency of the oscillator based on a phase of an output of the oscillator and a phase of the clock signal after the output of the oscillator and the clock signal are aligned. The delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Muhammad NUMMER, Dirk PFAFF
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Patent number: 8363488Abstract: In a method of operating a reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level, an oscillator sends requests for sampling and correction to a control block between accesses of the eDRAM. The control block sends a pulse defining a time interval during which sampling and correction occurs to a pulse generator. A reference generator provides the reference level to a comparator. The comparator compares the reference level with a sampling of a reference voltage to decide if the reference voltage requires correction. The comparator sends a correction request to a pulse generator if the reference voltage requires correction. The pulse generator generates a correction pulse for a driver according to the correction request from the comparator. The driver adjusts the reference voltage during the correction pulse.Type: GrantFiled: October 4, 2011Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Muhammad Nummer, Sergiy Romanovskyy
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Patent number: 8345498Abstract: A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor form cross coupled sensing pairs. The third PMOS and the fourth PMOS transistors serve as compensation transistors. The third NMOS and the fourth NMOS transistors serve as sensing enabling transistors.Type: GrantFiled: February 17, 2011Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sergiy Romanovskyy, Muhammad Nummer
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Publication number: 20120213015Abstract: A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor form cross coupled sensing pairs. The third PMOS and the fourth PMOS transistors serve as compensation transistors. The third NMOS and the fourth NMOS transistors serve as sensing enabling transistors.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sergiy ROMANOVSKYY, Muhammad NUMMER
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Publication number: 20120020170Abstract: In a method of operating a reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level, an oscillator sends requests for sampling and correction to a control block between accesses of the eDRAM. The control block sends a pulse defining a time interval during which sampling and correction occurs to a pulse generator. A reference generator provides the reference level to a comparator. The comparator compares the reference level with a sampling of a reference voltage to decide if the reference voltage requires correction. The comparator sends a correction request to a pulse generator if the reference voltage requires correction. The pulse generator generates a correction pulse for a driver according to the correction request from the comparator. The driver adjusts the reference voltage during the correction pulse.Type: ApplicationFiled: October 4, 2011Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Muhammad NUMMER, Sergiy ROMANOVSKYY
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Patent number: 8059475Abstract: A reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level includes an oscillator, a control block, a reference generator, a comparator, a pulse generator, a driver, and a reference voltage output, where the oscillator sends requests for sampling and correction to the control block between accesses of the eDRAM, the control block sends a pulse defining a time interval during which sampling and correction occurs to the pulse generator, the reference generator provides the reference level for comparison by the comparator with a sampling of the reference voltage output, the comparator decides if the reference voltage output requires correction and sends a correction request to the pulse generator if necessary, the pulse generator produces a correction pulse for the driver according to the correction request from the comparator, and the driver adjusts the reference voltage output during the correction pulse.Type: GrantFiled: June 9, 2010Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Muhammad Nummer, Sergiy Romanovskyy
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Publication number: 20100322019Abstract: A reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level includes an oscillator, a control block, a reference generator, a comparator, a pulse generator, a driver, and a reference voltage output, where the oscillator sends requests for sampling and correction to the control block between accesses of the eDRAM, the control block sends a pulse defining a time interval during which sampling and correction occurs to the pulse generator, the reference generator provides the reference level for comparison by the comparator with a sampling of the reference voltage output, the comparator decides if the reference voltage output requires correction and sends a correction request to the pulse generator if necessary, the pulse generator produces a correction pulse for the driver according to the correction request from the comparator, and the driver adjusts the reference voltage output during the correction pulse.Type: ApplicationFiled: June 9, 2010Publication date: December 23, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Muhammad NUMMER, Sergiy ROMANOVSKYY