Abstract: The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by a finite state machine (FSM) is operably connected to the microprocessor functional units and has a plurality of states that defines the operation of the microprocessor functional units. Each control state of the FSM implements the transfer of information between the registers of the datapath. The execution sequences through three states: an instruction fetch; an instruction decode; and instruction execute. The controller issues the required signals to the various hardware components to execute the instruction needed in three clock cycles.

Abstract: The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by a finite state machine (FSM) is operably connected to the microprocessor functional units and has a plurality of states that defines the operation of the microprocessor functional units. Each control state of the FSM implements the transfer of information between the registers of the datapath. The execution sequences through three states: an instruction fetch; an instruction decode; and instruction execute. The controller issues the required signals to the various hardware components to execute the instruction needed in three clock cycles.