Abstract: Several low power, low voltage swing, BiCMOS circuits for used in high speed chip-to-chip communications are described. In particular a BiCMOS low voltage swing transceiver comprising a driver and a receiver with low on-chip power consumption is reported. Operating at 3.3.V, the universal transceiver can drive and receive low voltage swing signals with termination voltages ranging from 5V down to 2V, without using external reference voltages and at frequencies exceeding 1 GHz. On-chip power consumption is much lower than that of known CML/ECL type transceivers having comparable speeds.

Abstract: A SRAM includes an ECL input buffer connected between an address bus and a W-OR predecoder array. The logic output of the W-OR predecoder array is applied to a level translator array and level shifted. The level shifted output of the level translator array is supplied to a plurality of self-resetting word-line decoder and driver (WLDD) circuits. The WLDD circuits supply activation pulses to selected blocks of memory in a memory cell array. Sense amplifiers sense and latch-in the data stored in the activated selected blocks of memory. The design of the W-OR predecoder array, level translator array, WLDD circuits and sense amplifiers is such to reduce the overall power consumption of the SRAM.