Abstract: A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.

Abstract: A field-programmable analog array (FPAA) includes a digital signal routing network, an analog signal routing network, switch elements to interconnect the digital signal routing network with the analog signal routing network, and a configurable analog block (CAB) connected to the analog signal routing network and having a programmable resistor array. The switch elements are implemented via digital memristors, the programmable resistor array is implemented via analog memristors, and/or antifuses within one or more of the digital signal routing network and the analog signal routing network are implemented via digital memristors.

Abstract: A programmable current-limited voltage buffer. The programmable current-limited voltage buffer includes at least one current-bias circuit, an inverter, a write-current set control circuit, and an adaptive current limiter. The inverter is coupled to the current-bias circuit and a reference-voltage source, and is configured to couple a row line to either the current-bias circuit, or the reference-voltage source, in response to an input signal. The adaptive current limiter is coupled to the current-bias circuit and to the write-current set control circuit, and is configured to limit current flowing through the memory element in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element during switching in an array of memory elements.

Abstract: A field-programmable analog array (FPAA) includes a digital signal routing network, an analog signal routing network, switch elements to interconnect the digital signal routing network with the analog signal routing network, and a configurable analog block (CAB) connected to the analog signal routing network and having a programmable resistor array. The switch elements are implemented via digital memristors, the programmable resistor array is implemented via analog memristors, and/or antifuses within one or more of the digital signal routing network and the analog signal routing network are implemented via digital memristors.

Abstract: A programmable current-limited voltage buffer 130-1. The programmable current-limited voltage buffer 130-1 includes at least one current-bias circuit 230-1, an inverter 230-2, a write-current set control circuit 230-3, and an adaptive current limiter 230-4. The inverter 230-2 is coupled to the current-bias circuit 230-1 and a reference-voltage source 178, and is configured to couple a row line 140-1 to either the current-bias circuit 230-1, or the reference-voltage source 178, in response to an input signal. The adaptive current limiter 230-4 is coupled to the current-bias circuit 230-1 and to the write-current set control circuit 230-3, and is configured to limit current flowing through the memory element 120-1 in a write operation. An integrated circuit device 110 is also provided, along with a method for current limiting a memory element 120-1 during switching in an array 120 of memory elements.

Abstract: A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

Abstract: A memory device capable of being sensed with an oscillating signal includes a first terminal of a memristive element connected to an oscillating signal supply, and a second terminal of the memristive element connected to sensing circuitry, the sensing circuitry to determine an attenuation of an oscillating signal from the oscillating signal supply. A crossbar array includes a first set of parallel lines selectively connected to an oscillating signal supply, a second set of parallel lines intersecting the first set of parallel lines, the second set of parallel lines selectively connected to sensing circuitry, memristive memory elements being disposed at crosspoints between the first set of parallel lines and the second set of parallel lines, in which a memory controller of the crossbar array is to determine a resistive state of one of the memory elements by determining, with the sensing circuitry, an attenuation of an oscillating signal produced by the oscillating signal supply.

Abstract: A memristor-protection integrated circuit. The memristor-protection integrated circuit includes a first current-bias circuit, a second current-bias circuit, an inverter, and a current limiter. The first and second current-bias circuits are configured to be coupled to first and second power-supply rails, respectively. The inverter is coupled to the first current-bias circuit and to the second current-bias circuit, and is configured to couple at least one memristor to at least one of the first current-bias circuit and the second current-bias circuit in response to an input signal applied to the inverter. The current limiter is coupled to the first current-bias circuit and coupled to the second current-bias circuit, and is configured to limit current flowing through the memristor.

Abstract: A memristor-protection integrated circuit. The memristor-protection integrated circuit includes a first current-bias circuit, a second current-bias circuit, an inverter, and a current limiter. The first and second current-bias circuits are configured to be coupled to first and second power-supply rails, respectively. The inverter is coupled to the first current-bias circuit and to the second current-bias circuit, and is configured to couple at least one memristor to at least one of the first current-bias circuit and the second current-bias circuit in response to an input signal applied to the inverter. The current limiter is coupled to the first current-bias circuit and coupled to the second current-bias circuit, and is configured to limit current flowing through the memristor.

Abstract: Biasing circuitry for generating and maintaining a substantially constant output bias current. Ratios of selected bias currents and selected transistor sizes ensure that a nominal load current is maintained notwithstanding variations in circuit fabrication processes, power supply voltage and operating temperature.