Abstract: Embodiments herein describe circuitry for mimicking SRAM cells. Instead of mimicking (or modeling) the entire SRAM cell, the mimic SRAM cells can mimic only the read path, which may include a pFET and two nFETs. In one embodiment, the mimic SRAM circuitry includes multiple selectable banks of mimic cells. During testing, the number of banks can be selected that best represent the worst case scenario—e.g., the PVT corner with the worst process variation. In addition to selecting the number of banks of mimic cells, the gate voltage of the transistors in the mimic cells can be adjusted.

Abstract: In an approach, a processor identifies a current cell depicted in an integrated circuit layout tool, the current cell of a hierarchical layout comprises a plurality of cells. A processor generates an overlay, the overlay comprising an abstraction of at least one object present in a higher level of the hierarchical layout that overlaps with the current cell. A processor projects the overlay onto the current cell.

Abstract: A computer-implemented method for layout versus schematic (LVS) checking for a design process of an integrated circuit (IC) is provided. The computer-implemented method includes receiving a layout of the IC at multiple hierarchical levels, receiving a schematic of the IC at the multiple hierarchical levels, establishing a requirement for name matching, scanning the layout and the schematic at least at one of the multiple hierarchical levels and issuing an alert for one or more name inconsistencies identified during the scanning.

Abstract: In an approach, a processor identifies a current cell depicted in an integrated circuit layout tool, the current cell of a hierarchical layout comprises a plurality of cells. A processor generates an overlay, the overlay comprising an abstraction of at least one object present in a higher level of the hierarchical layout that overlaps with the current cell. A processor projects the overlay onto the current cell.