Patents by Inventor Muhammad Umar CHOUDRY

Muhammad Umar CHOUDRY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037280
    Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Meghal Varia, Serag Gadelrab, Muhammad Umar Choudry
  • Patent number: 10007619
    Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Alexander Miretsky, Meghal Varia, Kyle John Ernewein, Manokanthan Somasundaram, Muhammad Umar Choudry, Serag Monier Gadelrab
  • Patent number: 9836158
    Abstract: Compensation for sensors in a touch and hover sensing device is disclosed. Compensation can be for sensor resistance and/or sensor sensitivity variation that can adversely affect touch and hover measurements at the sensors. To compensate for sensor resistance, the device can gang adjacent sensors together so as to reduce the overall resistance of the sensors. In addition or alternatively, the device can drive the sensors with voltages from multiple directions so as to reduce the effects of the sensors' resistance. To compensate for sensor sensitivity variation (generally at issue for hover measurements), the device can apply a gain factor to the measurements, where the gain factor is a function of the sensor location, so as to reduce the sensitivity variation at different sensor locations on the device.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: December 5, 2017
    Assignee: Apple Inc.
    Inventors: Brian Michael King, Omar S. Leung, Paul G. Puskarich, Jeffrey Traer Bernstein, Andrea Mucignat, Avi E. Cieplinski, Muhammad Umar Choudry, Praveen R. Subramani, Marc J. Piche, David Amm, Duncan Robert Kerr
  • Publication number: 20160350234
    Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
    Type: Application
    Filed: September 20, 2015
    Publication date: December 1, 2016
    Inventors: Jason Edward PODAIMA, Paul Christopher John WIERCIENSKI, Carlos Javier MOREIRA, Alexander MIRETSKY, Meghal VARIA, Kyle John ERNEWEIN, Manokanthan SOMASUNDARAM, Muhammad Umar CHOUDRY, Serag Monier GADELRAB
  • Publication number: 20160350225
    Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventors: Jason Edward PODAIMA, Paul Christopher John WIERCIENSKI, Kyle John ERNEWEIN, Carlos Javier MOREIRA, Meghal VARIA, Serag GADELRAB, Muhammad Umar CHOUDRY
  • Publication number: 20150169114
    Abstract: Compensation for sensors in a touch and hover sensing device is disclosed. Compensation can be for sensor resistance and/or sensor sensitivity variation that can adversely affect touch and hover measurements at the sensors. To compensate for sensor resistance, the device can gang adjacent sensors together so as to reduce the overall resistance of the sensors. In addition or alternatively, the device can drive the sensors with voltages from multiple directions so as to reduce the effects of the sensors' resistance. To compensate for sensor sensitivity variation (generally at issue for hover measurements), the device can apply a gain factor to the measurements, where the gain factor is a function of the sensor location, so as to reduce the sensitivity variation at different sensor locations on the device.
    Type: Application
    Filed: February 25, 2015
    Publication date: June 18, 2015
    Inventors: Brian Michael KING, Omar S. LEUNG, Paul G. PUSKARICH, Jeffrey Traer BERNSTEIN, Andrea MUCIGNAT, Avi E. CIEPLINSKI, Muhammad Umar CHOUDRY, Praveen R. SUBRAMANI, Marc J. PICHE, David AMM, Duncan Robert KERR