Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract: The present invention relates to specific markers capable of detecting the development of colorectal cancer and the colorectal cancer inhibitory effect of SeMet (selenomethionine) having a chemopreventive effect against colorectal cancer. When the expressions of the biomarkers according to the present invention are measured and the expression levels thereof are analyzed in combination, whether SeMet (selenomethionine) is to be administered to prevent colorectal cancer can be determined and the development of colorectal cancer and the inhibitory effect of SeMet (selenomethionine) against the development of colorectal cancer can be monitored. Thus, these markers can be effectively used to observe the colorectal cancer inhibitory effect of SeMet (selenomethionine) and the prognosis of colorectal cancer resulting from the intake of SeMet (selenomethionine).

Abstract: An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.

Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.

Abstract: A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.

Abstract: An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.

Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.

Abstract: An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.