Abstract: Certain aspects of the present disclosure are directed to a regulator. The regulator generally includes a source follower circuit and a low-voltage assist circuit. The low-voltage assist circuit generally includes a first transistor having a gate coupled to an output node of the source follower circuit, a voltage comparison circuit having a first input coupled to a source of the first transistor and a second input coupled to a control input node of the source follower circuit, and a second transistor having a gate coupled to an output of the voltage comparison circuit and a drain coupled to the output node of the source follower circuit.

Abstract: Techniques to identify a mechanism of action of a compound using network dysregulation are disclosed herein. An example method can include selecting at least a first interaction involving at least a first gene, determining a first n-dimensional probability density of gene expression levels for the first gene and one or more genes in a control state, determining a second n-dimensional probability density of gene expression levels for the first gene and one or more genes following treatment using at least one compound, estimating changes between the first probability density and the second probability density, and determining whether the estimated changes are statistically significant.

Abstract: Disclosed are methods, components, and systems for diagnosing, prognosing, and treating a cell proliferative disease or disorder such as cancer. The methods, components, and systems relate to identifying markers that may be utilized to diagnose and/or prognose a subject and optionally treat the diagnosed and/or prognosed subject by administering a topoisomerase poison to the subject based on the marker having been identified. Markers identified in the methods may include ribosomal subunit proteins and genes encoding ribosomal subunit proteins. Based on the marker being identified in the subject, the subject may be identified as having responsiveness to a topoisomerase poison, such as etoposide and/or doxombicin. As such, the subject may be treated by administering the topoisomerase poison to treat the cell proliferative disease or disorder after the marker has been identified.

Abstract: Techniques to identify a mechanism of action of a compound using network dysregulation are disclosed herein. An example method can include selecting at least a first interaction involving at least a first gene, determining a first n-dimensional probability density of gene expression levels for the first gene and one or more genes in a control state, determining a second n-dimensional probability density of gene expression levels for the first gene and one or more genes following treatment using at least one compound, estimating changes between the first probability density and the second probability density, and determining whether the estimated changes are statistically significant.

Abstract: Certain aspects of the present disclosure are directed to a regulator. The regulator generally includes a source follower circuit and a low-voltage assist circuit. The low-voltage assist circuit generally includes a first transistor having a gate coupled to an output node of the source follower circuit, a voltage comparison circuit having a first input coupled to a source of the first transistor and a second input coupled to a control input node of the source follower circuit, and a second transistor having a gate coupled to an output of the voltage comparison circuit and a drain coupled to the output node of the source follower circuit.

Abstract: A method for unbalancing a tri-level switching regulator uses hysteretic control when switching across multiple states of the tri-level switching regulator. The method includes determining a battery voltage and an output voltage of the tri-level switching regulator. The method also includes dynamically adjusting at least one of a first hysteretic window of a first hysteretic comparator associated with a second switching state of the tri-level switching regulator and a second hysteretic window of a second hysteretic comparator associated with a first switching state of the tri-level switching regulator based on the battery voltage and the output voltage.

Abstract: A method for unbalancing a tri-level switching regulator uses hysteretic control when switching across multiple states of the tri-level switching regulator. The method includes determining a battery voltage and an output voltage of the tri-level switching regulator. The method also includes dynamically adjusting at least one of a first hysteretic window of a first hysteretic comparator associated with a second switching state of the tri-level switching regulator and a second hysteretic window of a second hysteretic comparator associated with a first switching state of the tri-level switching regulator based on the battery voltage and the output voltage.

Abstract: A tri-level converter provides three levels of power supply to a power amplifier that includes a supply path. The supply path has a first transistor and a first inherent body diode associated with the first transistor, as well as a second transistor and a second inherent body diode associated with the second transistor. A polarity of the second body diode is reversed relative to a polarity of the first body diode. A first driver is configured to drive the first transistor and the first inherent body diode to control a power supply, including a battery supply signal, to an output of the tri-level converter. The tri-level converter is coupled to a switching node.

Abstract: Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.

Abstract: Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.

Abstract: Techniques to identify a mechanism of action of a compound using network dysregulation are disclosed herein. An example method can include selecting at least a first interaction involving at least a first gene, determining a first n-dimensional probability density of gene expression levels for the first gene and one or more genes in a control state, determining a second n-dimensional probability density of gene expression levels for the first gene and one or more genes following treatment using at least one compound, estimating changes between the first probability density and the second probability density, and determining whether the estimated changes are statistically significant.

Abstract: Exemplary embodiments are related to switching power converters. A switching power converter may comprise a plurality of control unit configured for average current mode control, wherein each control unit of the plurality comprises a dedicated proportional control unit. The switching power converter may further comprise an integrator coupled to each control unit of the plurality of control unit and configured to convey a signal to each control unit.

Abstract: A 3-gene prognostic panel has been identified that together accurately predicted the outcome of low Gleason score prostate tumors as either truly indolent or at a high risk of becoming aggressive. The 3-gene prognostic panel was validated on independent cohorts confirmed its independent prognostic value, as well as its ability to improve prognosis with currently used clinical nomograms. Expression of the 3-gene prognostic panel was determined by quantifying mRNA or protein encoded by the panel (collectively referred to as “prognostic biomarkers”). The prognostic biomarkers were discovered to be up-regulated in indolent tumors and down-regulated in aggressive forms of prostate cancer.

Abstract: Exemplary embodiments are related to switching power converters. A switching power converter may comprise a plurality of control unit configured for average current mode control, wherein each control unit of the plurality comprises a dedicated proportional control unit. The switching power converter may further comprise an integrator coupled to each control unit of the plurality of control unit and configured to convey a signal to each control unit.

Abstract: A semiconductor device having a low power mode includes a buffer circuit associated with an interface pad, a power management controller (PMC), and a wakeup unit for waking up a part of the device from the low power mode. The buffer circuit is disabled in the low power mode by asserting a power on reset (POR) signal associated with the PMC. A wakeup signal is generated and provided to the wakeup unit from an analog power supply associated with the buffer circuit.

Abstract: A semiconductor device having a low power mode includes a buffer circuit associated with an interface pad, a power management controller (PMC), and a wakeup unit for waking up a part of the device from the low power mode. The buffer circuit is disabled in the low power mode by asserting a power on reset (POR) signal associated with the PMC. A wakeup signal is generated and provided to the wakeup unit from an analog power supply associated with the buffer circuit.

Abstract: A power switch for an integrated circuit provides a stepped profile supply potential. A supply potential generation block generates the stepped profile output supply to control the ramp rate of the output in order to prevent a false trigger of electrostatic discharge at the pads of the integrated circuit.

Abstract: A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal.

Abstract: A power switch for an integrated circuit provides a stepped profile supply potential. A supply potential generation block generates the stepped profile output supply to control the ramp rate of the output in order to prevent a false trigger of electrostatic discharge at the pads of the integrated circuit.

Abstract: A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal.