Abstract: An Internet system for and method of automatic optimizing quantitative business objectives of sellers (advertisers) with synergistic pricing, promotions and advertisements, while simultaneously minimizing expenditure and discovery and optimizing allocation of advertising channels that optimize such objectives.

Abstract: An improved seller automated engine architecture methodology particularly (though not exclusively) for use in automated real-time iterative reverse auctions over the Internet and the like for the purchase and sale of goods and services, providing a choice of architectural implementations while enabling price optimization on market share-directed considerations, specific sales target-directed implementations, seller utility derivative-following implementations, model optimizer implementations and explorations, mathematical optimization-oriented and rules-based implementations.

Abstract: A method of communications network shopping by buyers of products and services for purchasing such from sellers in which buyers request an automatic reverse auctioneer or auction controller to initiate a reverse auction in real time amongst willing sellers and to solicit their automatic real-time iterative bidding price quotations for such products and services to be returned automatically over the network back to the controller under the iterative processing guidance of the controller to assure a best bid price quotation for the buyer; and automatically effecting buyer notification or purchase at such best price, all while the buyer may remain on-line, and without any manual intervention.

Abstract: A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

Abstract: A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

Abstract: A novel chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, data ports substantially symmetrically placed with each data port connected to each arbitration unit and each transmit/receive buffer bank, and with each data port enabled to write into any DRAM bank, with the connections being effected such that each data port is substantially symmetric with respect to DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed on the chip to minimize clock skew by symmetric clock distribution.

Abstract: Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Abstract: A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost. Through use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

Abstract: A novel architecture for high speed dual symmetric full duplex operation of otherwise asymmetrical telephone subscribers--central office modems that provide relatively high data rate downloading from the telephone central office but relatively low data rate uploading from the subscriber stations, whereby, through direction swapping by such duplex operation, equal downloading and uploading can be achieved, or other increasing or grate swapping or variation of the uploading rate capability, as desired. ADSL modems in particular, being reconfigured to provide symmetrical rate downloading and uploading and/or configured direction assignment of rates.

Abstract: A technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only "on-the-fly" alterable chip and similar device reconfigurations, but, where desired, self-modifying reconfigurations for differing functionalities of the devices, eliminating current serious reconfigurability limitations and related problems, while providing significantly enhanced system performance at low cost. A large amount of memory is available internal to the FPGA and is accessed with a small number of pins such that the reconfiguration time is, for example, four orders of magnitude faster than the traditional approaches and at notably low cost.

Abstract: A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost through the use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

Abstract: A method of and apparatus for improving the accessing capability of asynchronous and synchronous dynamic random access memory devices by a novel interfacing and accessing procedure in which the same pins are used for each of row, column and data accessing and in both the write and read cycles; such enabling effective increasing of the data bandwidth and addressing range in substantially the same size packages and pin counts of current DRAMs, or providing equivalent performance in smaller packages with fewer pins. This enables reducing the number of required components for the same configuration, providing compatable density in smaller packages, and with lower power consumption and finer granularity and pin compatability for a wide range of current DRAMs.