Abstract: In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system.

Abstract: A memory device incorporating a multi-media accelerator and an embedded memory, wherein the memory device operates as a standard stand-alone memory when the multi-media accelerator is not enabled. The memory device includes a memory interface that is compatible with multiple types of memory controllers, thereby enabling multiple types of external devices to interact with the multi-media accelerator and access the embedded memory. The embedded memory can be shared between external devices and multi-media devices.

Abstract: In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system.

Abstract: A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.

Abstract: A hardware Java™ accelerator is provided to implement portions of the Java™ virtual machine in hardware in order to accelerate the operation of the system on Java™ bytecodes. The Java™ hardware accelerator preferably includes Java™ bytecode translation into native CPU instructions. The combination of the Java™ hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java™ programs for use in commercial appliances.

Abstract: A Java accelerator includes a hardware unit associated with the CPU portion, the hardware unit converting stack-based instructions, such as Java bytecodes, into register-based instructions such as the instructions which are native to the CPU. A thread lifetime unit in the hardware unit is used to maintain a count of the number of bytecodes to be executed while an active thread is loaded into the system. Once this count reaches zero or below, the operation of a/the thread in the system is stopped and the Java Virtual Machine loaded into the CPU portion in order to implement its thread manager. Additionally, a single step unit in the hardware unit allows the production of debugger indications after each stack-based instruction.

Abstract: A system for implementing Java methods is described in which a Java virtual machine replaces normal method invocation instructions with custom method invocation instructions which are recognized by a hardware translator. The hardware translator can then use stored instructions from a microcode unit to cause a processor to set up a special hardware unit.

Abstract: In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes. The Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions. The combination of the Java hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java programs for use in commercial appliances.

Abstract: A Java accelerator includes a hardware unit associated with the CPU portion, the hardware unit converting stack-based instructions, such as Java bytecodes, into register-based instructions such as the instructions which are native to the CPU. A thread lifetime unit in the hardware unit is used to maintain a count of the number of bytecodes to be executed while an active thread is loaded into the system. Once this count reaches zero or below, the operation of a/the thread in the system is stopped and the Java Virtual Machine loaded into the CPU portion in order to implement its thread manager. Additionally, a single step unit in the hardware unit allows the production of debugger indications after each stack-based instruction.

Abstract: An implementation of Java is disclosed in which references to the constant pool are implemented by using a Data Resolution Field within the constant pool entry. The Data Resolution Field acts as an index to a jump table to jump to resolve the reference or to perform the bytecode instruction. When the reference is resolved, the contents of the Data Resolution Field in the constant pool entry are modified so that the next time the bytecode is run, the resolution steps need not be done.

Abstract: A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes. The Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions. The combination of the Java hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java programs for use in commercial appliances.