Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.

Abstract: An SOI circuit configuration effective for minimizing plasma-induced charging damage during fabrication comprises the formation of charge collectors connected to the gate electrode and the semiconductor body, wherein each one of the charge collectors have the same or substantially the same shape and dimension. A connecting structure formed between a device fabricated on SOI substrate and substrate is delayed until the latter stages of processing.