Abstract: Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

Abstract: Devices and methods are disclosed for detecting which of a multiple ports of a storage device is connected to a host system using a shared detection line. In certain embodiments, a storage device includes non-volatile memory, a first data port, a second data port having a faster data transfer speed, a shared detection line, and control circuitry. The control circuitry can be configured to detect voltage on the shared detection line in response to a connection of at least one of the first data port and the second data port to the host system, determine which of the first data port or the second data port is connected to the host system, and establish a data connection with the host system at the first data transfer speed or the second data transfer speed based on the port connected to the host system.

Abstract: Devices and methods are disclosed for detecting which of a multiple ports of a storage device is connected to a host system using a shared detection line. In certain embodiments, a storage device includes non-volatile memory, a first data port, a second data port having a faster data transfer speed, a shared detection line, and control circuitry. The control circuitry can be configured to detect voltage on the shared detection line in response to a connection of at least one of the first data port and the second data port to the host system, determine which of the first data port or the second data port is connected to the host system, and establish a data connection with the host system at the first data transfer speed or the second data transfer speed based on the port connected to the host system.