Patents by Inventor Mukesh Nair
Mukesh Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9466599Abstract: An input/output (IO) circuit including: an IO driver circuit; an electrostatic discharge (ESD) protection semiconductor switch with a first input configured to receive an ESD, a second input connected to an ESD rail, and a switch control input; an ESD trigger circuit connected to the switch control input, wherein the ESD trigger circuit is configured to produce a trigger signal to close the protection semiconductor switch when the ESD detection circuit detects an ESD; and a bias circuit configured to provide a back bias signal to an isolated well of the ESD protection semiconductor switch when IO circuit is in normal operation.Type: GrantFiled: September 18, 2013Date of Patent: October 11, 2016Assignee: NXP B.V.Inventor: Mukesh Nair
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Publication number: 20150077887Abstract: An input/output (IO) circuit including: an IO driver circuit; an electrostatic discharge (ESD) protection semiconductor switch with a first input configured to receive an ESD, a second input connected to an ESD rail, and a switch control input; an ESD trigger circuit connected to the switch control input, wherein the ESD trigger circuit is configured to produce a trigger signal to close the protection semiconductor switch when the ESD detection circuit detects an ESD; and a bias circuit configured to provide a back bias signal to an isolated well of the ESD protection semiconductor switch when IO circuit is in normal operation.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: NXP B.V.Inventor: Mukesh NAIR
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Patent number: 8866454Abstract: ADC-DC converter, for a solar charger, is disclosed. The converter is based on a buck-boost converter, and is operable both in a boost mode, and in a buck mode. The converter differs from known converters, in that during buck mode operation, the boost mode is disabled, thereby reducing or eliminating the losses associated with buck mode operation. Methods of operating such a reconfigurable buck-boost converter are also disclosed as is a computer programme product for controlling a reconfigurable buck-boost converter.Type: GrantFiled: January 11, 2011Date of Patent: October 21, 2014Assignee: NXP B.V.Inventor: Mukesh Nair
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Patent number: 8629647Abstract: A battery charger, or charge controller, for a photovoltaic system is disclosed, comprising a maximum power point tracker (MPPT) circuit, which may be bypassed by means of a bypass circuit. The bypass circuit may be a simple electrical wire or link. The battery charger is operable to track the maximum power of a photogenerator by means of the MPPT, or to bypass the MPPT and disable it, in dependence on whether the power loss which results from the MPPT would be greater than the power saving achieved by tracking the maximum power point of the photogenerator. Also disclosed is a control unit for use in such a battery charger, and a method for controlling such a battery charger.Type: GrantFiled: July 29, 2010Date of Patent: January 14, 2014Assignee: NXP, B.V.Inventors: Dattatreya Bhat, Mukesh Nair, Nagavolu Srinivasa Murty, Vasu Poojary
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Publication number: 20120319667Abstract: ADC-DC converter, for a solar charger, is disclosed. The converter is based on a buck-boost converter, and is operable both in a boost mode, and in a buck mode. The converter differs from known converters, in that during buck mode operation, the boost mode is disabled, thereby reducing or eliminating the losses associated with buck mode operation. Methods of operating such a reconfigurable buck-boost converter are also disclosed as is a computer programme product for controlling a reconfigurable buck-boost converter.Type: ApplicationFiled: January 11, 2011Publication date: December 20, 2012Applicant: NXP B.V.Inventor: Mukesh Nair
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BATTERY CHARGER FOR A PHTOVOLTAIC SYSTEM, A CONTROLLER THEREFOR AND A METHOD OF CONTROLLING THE SAME
Publication number: 20110031926Abstract: A battery charger, or charge controller, for a photovoltaic system is disclosed, comprising a maximum power point tracker (MPPT) circuit, which may be bypassed by means of a bypass circuit. The bypass circuit may be a simple electrical wire or link. The battery charger is operable to track the maximum power of a photogenerator by means of the MPPT, or to bypass the MPPT and disable it, in dependence on whether the power loss which results from the MPPT would be greater than the power saving achieved by tracking the maximum power point of the photogenerator. Also disclosed is a control unit for use in such a battery charger, and a method for controlling such a battery charger.Type: ApplicationFiled: July 29, 2010Publication date: February 10, 2011Applicant: NXP B.V.Inventors: Dattatreya Bhat, Mukesh Nair, Nagavolu Srinivasa Murty, Vasu Poojary -
Patent number: 7772875Abstract: An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and second switch (T1, T2; T4, T5). The buffer is arranged in a second supply voltage domain (VDD1, GND1). Furthermore, a control circuit is coupled to the buffer for controlling the first and second switch (T1, T2; T4, T5) such that during a transition of an input signal of the input/output circuit (10) both switches (T1, T2; T4, T5) are temporarily kept in a conducting state and a crowbar current flows through the buffer (INV).Type: GrantFiled: December 18, 2006Date of Patent: August 10, 2010Assignee: NXP B.V.Inventor: Mukesh Nair
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Publication number: 20080272799Abstract: An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and second switch (T1, T2; T4, T5). The buffer is arranged in a second supply voltage domain (VDD1, GND1). Furthermore, a control circuit is coupled to the buffer for controlling the first and second switch (T1, T2; T4, T5) such that during a transition of an input signal of the input/output circuit (10) both switches (T1, T2; T4, T5) are temporarily kept in a conducting state and a crowbar current flows through the buffer (INV).Type: ApplicationFiled: December 18, 2006Publication date: November 6, 2008Applicant: NXP B.V.Inventor: Mukesh Nair
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Patent number: 6690222Abstract: A multiple voltage environment input pad with a circuit input comprises a level shifter circuit (A) and a buffer circuit (B). The buffer circuit B comprises an inverter comprising at least two transistors (6, 7) of opposite types, followed by twin controllable voltage dividers (8, 10; 4, 5, 9) of opposite types. Each controllable voltage divider (8, 10; 4, 5, 9) has at least two controllable voltage divider inputs and a controllable voltage divider output. For each of the controllable voltage dividers (8, 10; 4, 5, 9) one of the inputs is connected to an output (16) of the level shifter circuit (A) and another one of the inputs is connected to an output (14) of the inverter. For each of the controllable voltage dividers (8, 10; 4, 5, 9) the voltage divider output is connected to a current input connection of a transistor (6, 7) of corresponding type of the inverter. The level shifter circuit (A) comprises a series pass transistor (2) and in parallel thereto a transistorized capacitor (15).Type: GrantFiled: June 19, 2002Date of Patent: February 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Mukesh Nair
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Publication number: 20030001645Abstract: A multiple voltage environment input pad with a circuit input comprises a level shifter circuit (A) and a buffer circuit (B). The buffer circuit B comprises an inverter comprising at least two transistors (6, 7) of opposite types, followed by twin controllable voltage dividers (8, 10; 4, 5, 9) of opposite types. Each controllable voltage divider (8, 10; 4, 5, 9) has at least two controllable voltage divider inputs and a controllable voltage divider output. For each of the controllable voltage dividers (8, 10; 4, 5, 9) one of the inputs is connected to an output (16) of the level shifter circuit (A) and another one of the inputs is connected to an output (14) of the inverter. For each of the controllable voltage dividers (8, 10; 4, 5, 9) the voltage divider output is connected to a current input connection of a transistor (6, 7) of corresponding type of the inverter. The level shifter circuit (A) comprises a series pass transistor (2) and in parallel thereto a transistorized capacitor (15).Type: ApplicationFiled: June 19, 2002Publication date: January 2, 2003Inventor: Mukesh Nair