Abstract: A ball grid technology circuit assembly for mounting and connecting a ball grid array circuit package having a grid array of ball pads to a printed circuit board and providing enhanced connections for testing of the ball grid array circuits. The printed circuit board includes a via array of vias wherein each via extends from the upper face of the printed circuit board to a lower face of the printed circuit board and is co-located with a ball pad of the ball grid array to provide a path between the ball pad and the lower end of the via to provide electrical access to the corresponding ball pad. A probe array includes a pin array of probe pins wherein each probe pin is co-located with a via of the via array to provide electrical contact with a ball pad of the ball grid array.

Abstract: A low inductance integrated circuit package such as a ball grid array having mounting conductors formed on a first side thereof and a die attachment region formed on second side thereof. A plurality of conductors internal to the package interconnect the mounting conductors to the die attachment region. A plurality of diagnostic contact pads are connected to the conductors and configured for ready access by a test probe. The contact pads are preferably provided at a periphery of the package.

Abstract: An improved bucket brigade circuit is disclosed having an improved transfer efficiency and dynamic range. Conventional bucket brigade circuits consist of a chain of storage capacitors and charge transfer circuits functioning as an analog shift register. Due to the nodal capacitance at the first load of prior art circuits, the charge thereon cannot be maintained at an optimum level because of voltage pull-back and charge redistribution during the fall time of the clock pulse. The invention disclosed herein provides an additional capacitor connecting the first node of the circuit to the inverse of the clock waveform, thereby eliminating the voltage pull-back and charge redistribution problem, resulting in an improved charge transfer efficiency and dynamic range for the circuit.