Patents by Inventor Mukesh V. Khare
Mukesh V. Khare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8785281Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: GrantFiled: February 9, 2012Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
-
Patent number: 8507992Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: GrantFiled: March 15, 2011Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
-
Publication number: 20120142181Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: ApplicationFiled: February 9, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
-
Patent number: 8193099Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.Type: GrantFiled: March 17, 2011Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Renee T. Mo, Ravikumar Ramachandran, Richard S. Wise, Hongwen Yan
-
Patent number: 8158481Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: GrantFiled: January 7, 2010Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
-
Publication number: 20110156158Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: ApplicationFiled: March 15, 2011Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
-
Patent number: 7943460Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: GrantFiled: April 20, 2009Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
-
Publication number: 20100264495Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: ApplicationFiled: April 20, 2009Publication date: October 21, 2010Applicant: International Business Machines CorporationInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
-
Publication number: 20100112800Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
-
Patent number: 7671421Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: GrantFiled: May 31, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
-
Patent number: 7109559Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: GrantFiled: November 5, 2004Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, James J. Quinlivan, Beth A. Ward
-
Patent number: 6893979Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: GrantFiled: March 15, 2001Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, James J. Quinlivan, Beth A. Ward
-
Patent number: 6635517Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.Type: GrantFiled: August 7, 2001Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta, Paul A. Ronsheim, Ghavam G. Shahidi
-
Patent number: 6569781Abstract: A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.Type: GrantFiled: January 22, 2002Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Richard D. Kaplan, Mukesh V. Khare, Suryanarayan G. Hegde
-
Publication number: 20030032251Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta, Paul A. Ronsheim, Ghavam G. Shahidi
-
Publication number: 20020130377Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, J. J. Quinlivan, Beth A. Ward
-
Patent number: 6096580Abstract: A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.Type: GrantFiled: September 24, 1999Date of Patent: August 1, 2000Assignee: International Business Machines CorporationInventors: S. Sundar Kumar Iyer, Liang-Kai Han, Robert Hannon, Subramanian S. Iyer, Mukesh V. Khare