Abstract: A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICs) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs.

Abstract: In accordance with embodiments of the present disclosure, a method may include determining if personality information associated with an information handling resource of an information handling system is present on a personality module of the information handling system. The method may also include modifying the information handling resource or a second information handling resource to include the personality information in response to determining that the personality information associated with the information handling resource is present in the personality module. The method may further include executing the information handling resource or the second information handling resource as modified with the personality information.

Abstract: A method may include generating a first shared secret for a present boot session of the information handling system and determining if a second shared secret existed for a prior boot session of the information handling system. If the second shared secret existed for the prior boot session, the method may include encrypting the first shared secret with the second shared secret and communicating the first shared secret encrypted by the second shared secret from a first information handling resource to a second information handling resource. If the second shared secret did not exist for the prior boot session, the method may include communicating the first shared secret unencrypted from the first information handling resource to the second information handling resource. The method may additionally include securely communicating between the first information handling resource and the second information handling resource using the first shared secret for encryption and decryption.

Abstract: In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin.

Abstract: A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICs) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs.

Abstract: A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICS) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICS) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs.

Abstract: A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root port width is greater than the device lane width then the root port is dynamically configured via hardware strapping to include a predefined number of adjacent ports with each port having a lane width equal to the device lane width. The root port is reset to force training of the first device and the second device.

Abstract: A method for translating a system address includes providing a first system address to a firmware and retrieving a first translation data corresponding to a memory configuration from storage. The first system address is translated into a first physical location utilizing the first translation data, and the first physical location is outputted.

Abstract: A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root port width is greater than the device lane width then the root port is dynamically configured via hardware strapping to include a predefined number of adjacent ports with each port having a lane width equal to the device lane width. The root port is reset to force training of the first device and the second device.

Abstract: The present invention provides a BIOS having two sets of flags. The first set of flags is the build capability flags. The second set of flags is the boot capability flags. Each of the flags can be stored as a value through the combination of bits that make up the flags and are stored in, for example, a register. The one or more values that make up the build capability flags can be compared to the one or more values that make up the boot capability flags. The current BIOS is updateable with a BIOS version that also has a build capability flag and a current boot capability flag. More specifically, the BIOS is updateable if the replacement build capability flags enable the booting of an information system having current build capability. For example, an update of the BIOS will only occur if the value of the updated build capability flags is greater than or equal to the value of the current boot capability flags.

Abstract: A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root port width is greater than the device lane width then the root port is dynamically configured via hardware strapping to include a predefined number of adjacent ports with each port having a lane width equal to the device lane width. The root port is reset to force training of the first device and the second device.

Abstract: An information handling system is provided with a BIOS and a baseboard management controller. The baseboard management controller is provided with non-standard functionality that enables the BIOS to request sensor data records of a specific type. Thus the BIOS can ask for specific kinds of sensor data, such as those for memory sensors only.

Abstract: A system and method for tracking bootable devices are disclosed which provide significant advantages over current computer system device management techniques. A system incorporating teachings of the present disclosure may include one or more installed bootable devices and a computer readable medium storing identification data for each of the installed bootable devices. The identification data may include host bridge identification data.

Abstract: A system and method for handling number power management signals, such as PME# signals, is disclosed. The power management signal lines are coupled to general purpose inputs in the south bridge or super I/O. The general purpose input that received the power management signal records the assertion of a power management signal. A logical circuit is employed to logically OR the power management signals to a single dedicated power management signal input so that the computer system will power up if any PCI device asserts a power management signal. The BIOS records the identity of the general purpose that received the power management signal in a memory location associated with that general purpose input or as a virtualized power management signal input. The operating system checks the memory location or virtualized power management signal input to determine which power management signal line transmitted the power management signal.

Abstract: An apparatus and method are disclosed for reducing the amount of time to execute a boot sequence, such as a power-on self-test (POST) routine, by eliminating a scan for devices interfaced with a local bus associated with a computer system. A detection circuit interfaces with a card slot through the local bus and generates a status bit indicating whether the configuration of devices for the computer system changed after completion of a first boot sequence. A processor interfaces with the local bus and reads the status bit during a second boot sequence. If the status bit indicates that the computer system device configuration remains the same, the processor eliminates the scan for devices interfaced with the computer system.

Abstract: A system and method for handling number power management signals, such as PME# signals, is disclosed. The power management signal lines are coupled to general purpose inputs in the south bridge or super I/O. The general purpose input that received the power management signal records the assertion of a power management signal. A logical circuit is employed to logically OR the power management signals to a single dedicated power management signal input so that the computer system will power up if any PCI device asserts a power management signal. The BIOS records the identity of the general purpose that received the power management signal in a memory location associated with that general purpose input or as a virtualized power management signal input. The operating system checks the memory location or virtualized power management signal input to determine which power management signal line transmitted the power management signal.