Patents by Inventor Mukund Pushottam Khatri

Mukund Pushottam Khatri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017071
    Abstract: An information handling system includes a processor, a peripheral component interconnect express (PCIe) endpoint, and a PCIe downstream port. The PCIe downstream port blocks PCIe vendor-defined messages (VDMs) from the PCIe endpoint as a default mode, changes to a second mode in response to the PCIe endpoint being verified, and allows PCIe VDMs from the PCIe endpoint while in the second mode.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 25, 2021
    Assignee: Dell Products L.P.
    Inventors: Austin P. Bolen, Mukund Pushottam Khatri, Kevin T. Marks, Manjunath Am
  • Patent number: 10990680
    Abstract: An information handling system includes a memory to store BIOS, a processor, a BMC, and an add-in device. The BMC updates the BIOS in a first system state and prevents BIOS updates in a second system state. The add-in device is configured to update firmware in a first device state and to prevent firmware updates in a second device state. The add-in device enters the first device state when the add-in device receives a power-on reset. The add-in device receives a lockdown command, sets the add-in device to the second device state in response to the lockdown command, and prevents the add-in device from reentering the first device state until the add-in device receives a second power-on reset subsequent to the first power-on reset.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Lee E. Ballard, Mukund Pushottam Khatri, Jonathan F. Lewis
  • Publication number: 20200042692
    Abstract: An information handling system includes a processor, a peripheral component interconnect express (PCIe) endpoint, and a PCIe downstream port. The PCIe downstream port blocks PCIe vendor-defined messages (VDMs) from the PCIe endpoint as a default mode, changes to a second mode in response to the PCIe endpoint being verified, and allows PCIe VDMs from the PCIe endpoint while in the second mode.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 6, 2020
    Inventors: Austin P. Bolen, Mukund Pushottam Khatri, Kevin T. Marks, Manjunath AM
  • Publication number: 20200034541
    Abstract: An information handling system includes a memory to store BIOS, a processor, a BMC, and an add-in device. The BMC updates the BIOS in a first system state and prevents BIOS updates in a second system state. The add-in device is configured to update firmware in a first device state and to prevent firmware updates in a second device state. The add-in device enters the first device state when the add-in device receives a power-on reset. The add-in device receives a lockdown command, sets the add-in device to the second device state in response to the lockdown command, and prevents the add-in device from reentering the first device state until the add-in device receives a second power-on reset subsequent to the first power-on reset.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Inventors: Lee E. Ballard, Mukund Pushottam Khatri, Jonathan F. Lewis