Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Abstract: Disclosed embodiments relate to enhanced auto-precharge memory scheduling. In one example, a system includes a memory having a matrix of storage cells, which, responsive to a row address strobe (RAS) signal, activates a given row, responsive to a column address strobe (CAS) signal, selects storage cells in the given row, and, responsive to a combined auto-precharge (AP) and CAS signal, accesses, then closes the given row. A memory controller selects a memory request from a memory request queue, generates the RAS signal to activate a row, when another memory request to the row is enqueued, generates the CAS signal to select a storage cell, when another memory request to a same bank but a different row is enqueued, generates the combined AP and CAS signal, and, when no memory request to the same bank is enqueued, generates the CAS signal only, allowing a close timer to close the row.

Abstract: Disclosed embodiments relate to enhanced auto-precharge memory scheduling. In one example, a system includes a memory having a matrix of storage cells, which, responsive to a row address strobe (RAS) signal, activates a given row, responsive to a column address strobe (CAS) signal, selects storage cells in the given row, and, responsive to a combined auto-precharge (AP) and CAS signal, accesses, then closes the given row. A memory controller selects a memory request from a memory request queue, generates the RAS signal to activate a row, when another memory request to the row is enqueued, generates the CAS signal to select a storage cell, when another memory request to a same bank but a different row is enqueued, generates the combined AP and CAS signal, and, when no memory request to the same bank is enqueued, generates the CAS signal only, allowing a close timer to close the row.

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.