Abstract: A rate limiter incorporated in a server connected to a network. The rate limiter is adapted to reduce congestion in the network in response to a congestion notification message. The server is adapted to send packets over the network. The rate limiter includes at least one of: a server rate limiter engine adapted to rate limit the packets in response to the server; a virtual machine rate limiter engine adapted to rate limit the packets in response to a virtual machine associated with the packets, the virtual machine hosted by the server; a flow rate limiter engine adapted to rate limit the packets in response to a flow associated with the packets; the flow being one of a plurality of flows transporting packets over the network; and a transmit engine adapted to rate limit the packets in response to a virtual pipe of the network for transmitting the packets.

Abstract: An intelligent network processor is disclosed that provides a PCI express (PCIe) host bus adapter with firmware selectable hardware capabilities and firmware enabled emulation of capabilities not supported by hardware. Support for Fibre Channel (FC) and Gigabit Ethernet (GbE) protocols are provided through the same fabric ports, including multiple port trunking for both protocols. On chip protocol conversion is provided for switching and routing between FC and GbE ports. Switching using the same crossbar module is provided for both FC and GbE protocols. The crossbar module is coupled to directly access external DDR memory so that messages from FC, GbE, and PCIe interfaces may be switched directly to the DDR memory.

Abstract: A rate limiter incorporated in a server connected to a network. The rate limiter is adapted to reduce congestion in the network in response to a congestion notification message. The server is adapted to send packets over the network. The rate limiter includes at least one of: a server rate limiter engine adapted to rate limit the packets in response to the server; a virtual machine rate limiter engine adapted to rate limit the packets in response to a virtual machine associated with the packets, the virtual machine hosted by the server; a flow rate limiter engine adapted to rate limit the packets in response to a flow associated with the packets; the flow being one of a plurality of flows transporting packets over the network; and a transmit engine adapted to rate limit the packets in response to a virtual pipe of the network for transmitting the packets.

Abstract: A storage processor is constructed on or within an interconnected circuit (IC) chip. The storage processor has a plurality of ports operable to send and/or receive messages to/from storage devices. An output indication circuit is associated with each output port. The indication circuit indicates that data is ready to be transmitted to a storage device from the particular output port. A crossover circuit is interposed between the ports. The crossover circuit has a memory that can store data. When data is received at a port, the storage processor can store the incoming data to the crossover circuit. A memory is also present on the chip. The memory holds data that relates incoming data to outgoing data. Thus, when data comes into the storage processor, the storage processor can determine a specific course of action for that data based upon the information stored in this memory. The chip also has a plurality of processing sub-units coupled to the crossover switch.