Abstract: The present invention discloses a method for extracting a trap time constant of a gate dielectric layer in a semiconductor device, which is related to the reliability of microelectronic devices. The method comprises initializing a state of a trap in the semiconductor device so that the trap finally comes to an empty state; applying a DC or AC signal to a gate terminal and a zero bias Vd1 to a drain terminal; after a period of time t1, applying small voltages Vg2 and Vd2 to the gate and drain terminals respectively, and detecting a state of a drain current Id; modifying the time t1 to t2=t1+?t while maintaining other conditions; repeatedly performing the previous steps in a same manner to perform N times of measurements for N numbers of time points t1, t1+?t, . . .