Abstract: Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

Abstract: Disclosed are a slew boost amplifier and a display driver having the same, which include a first current generation circuit configured to apply a first current to an upper current mirror circuit, a second current generation circuit configured to apply a second current to a lower current mirror circuit, and a comparison circuit configured to detect a difference between an input voltage and an output voltage and to apply the first current when the difference is greater than or equal to a first predetermined threshold and the second current generation circuit to apply the second current when the difference is less than a second predetermined threshold.

Abstract: Disclosed are a slew boost amplifier and a display driver having the same, which include a first current generation circuit configured to apply a first current to an upper current mirror circuit, a second current generation circuit configured to apply a second current to a lower current mirror circuit, and a comparison circuit configured to detect a difference between an input voltage and an output voltage and to apply the first current when the difference is greater than or equal to a first predetermined threshold and the second current generation circuit to apply the second current when the difference is less than a second predetermined threshold.

Abstract: Disclosed is an amplifier having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a slew rate improvement circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a first slew rate improvement circuit, and a second slew rate improvement circuit.

Abstract: Disclosed is an amplifier capable of minimizing short-circuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

Abstract: An output amplifier includes an input unit including first and second input transistors, and a first bias transistor between a connection node of a source of the first input transistor and a source of the second input transistor and a first voltage source, a first current mirror including first and second transistors connected in series at a first connection node and between a second voltage source and a second connection node, and third and fourth transistors connected in series at a third connection node and between the second voltage source and a fourth connection node, and a second current mirror including fifth and sixth transistors between a fifth connection node and the first voltage source and connected in series at a sixth connection node, and seventh and eighth transistors between a seventh connection node and the first voltage source.

Abstract: A half-power buffer amplifier is disclosed. The amplifier includes an amplification unit configured to differentially amplify differential input signals, the amplification unit including nodes configured to output differentially amplified first to fourth output signals, a first output buffer unit including first and second transistors, and an output node to which the first and second transistors are connected, a second output buffer unit including third and fourth transistors, wherein the third and fourth transistors are connected to the output node, a first control switch between the first output node and the second transistor and controlled by a polarity control signal, and a second control switch between the second output node and the third transistor and controlled by a complement of the polarity control signal.

Abstract: An output buffer circuit is disclosed to achieve a high slew rate without increasing current consumption. The output buffer circuit includes an input circuit configured to output a first signal and a second signal in response to an input signal, and a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal to control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal.

Abstract: An output buffer circuit is disclosed to achieve a high slew rate without increasing current consumption. The output buffer circuit includes an input circuit configured to output a first signal and a second signal in response to an input signal, and a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal to control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal.

Abstract: An output amplifier includes an input unit including first and second input transistors, and a first bias transistor between a connection node of a source of the first input transistor and a source of the second input transistor and a first voltage source, a first current mirror including first and second transistors connected in series at a first connection node and between a second voltage source and a second connection node, and third and fourth transistors connected in series at a third connection node and between the second voltage source and a fourth connection node, and a second current mirror including fifth and sixth transistors between a fifth connection node and the first voltage source and connected in series at a sixth connection node, and seventh and eighth transistors between a seventh connection node and the first voltage source.

Abstract: Disclosed is a gamma correction circuit and method capable of minimizing power consumption by adding third and fourth input amplifiers receiving reference voltages which are identical to voltages to first and second input amplifiers, respectively, and deactivating the first and second input amplifiers during an always on display (AOD) mode. The gamma correction circuit includes a first input amplifier configured to output a maximum voltage when active, a second input amplifier configured to output a minimum voltage when active, a third input amplifier configured to output a highest gamma voltage in response to the first reference voltage, and a fourth input amplifier configured to output a lowest gamma voltage in response to the second reference voltage. The first and second input amplifiers are deactivated when the display driving device operates in the AOD mode.

Abstract: A half-power buffer amplifier is disclosed. The amplifier includes an amplification unit configured to differentially amplify differential input signals, the amplification unit including nodes configured to output differentially amplified first to fourth output signals, a first output buffer unit including first and second transistors, and an output node to which the first and second transistors are connected, a second output buffer unit including third and fourth transistors, wherein the third and fourth transistors are connected to the output node, a first control switch between the first output node and the second transistor and controlled by a polarity control signal, and a second control switch between the second output node and the third transistor and controlled by a complement of the polarity control signal.

Abstract: Disclosed is a gamma correction circuit and method capable of minimizing power consumption by adding third and fourth input amplifiers receiving reference voltages which are identical to voltages to first and second input amplifiers, respectively, and deactivating the first and second input amplifiers during an always on display (AOD) mode. The gamma correction circuit includes a first input amplifier configured to output a maximum voltage when active, a second input amplifier configured to output a minimum voltage when active, a third input amplifier configured to output a highest gamma voltage in response to the first reference voltage, and a fourth input amplifier configured to output a lowest gamma voltage in response to the second reference voltage. The first and second input amplifiers are deactivated when the display driving device operates in the AOD mode.

Abstract: A half-power buffer and/or amplifier is disclosed. The half-power buffer and/or amplifier includes an amplifying unit including first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and a first output node configured to connect the first and second transistors and to output a voltage over a first voltage range between the first and third voltages, a second output buffer unit including third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and a second output node configured to connect the third and fourth transistors and to output a voltage over a second voltage range between the second and third voltages, and a first charge share switch unit connected between the gate of the second transistor and the first voltage source, and configured to perform a charge share and/or equalization operation.

Abstract: A half-power buffer and/or amplifier is disclosed. The half-power buffer and/or amplifier includes an amplifying unit including first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and a first output node configured to connect the first and second transistors and to output a voltage over a first voltage range between the first and third voltages, a second output buffer unit including third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and a second output node configured to connect the third and fourth transistors and to output a voltage over a second voltage range between the second and third voltages, and a first charge share switch unit connected between the gate of the second transistor and the first voltage source, and configured to perform a charge share and/or equalization operation.

Abstract: Disclosed is a half-power buffer/amplifier. The half-power buffer/amplifier includes first and second amplifying blocks respectively corresponding to first and second channels, a first output buffer unit controlled by an output from the first amplifying block, and a second output buffer unit controlled by an output from the second amplifying block. Each of the first and second amplifying blocks includes an input unit configured to amplify a first input signal, thereby outputting first and second currents, and an amplifying unit including a first current mirror, a second current mirror, and a bias unit connected between the first current mirror and the second mirror. Nodes in the first and second amplifying blocks are selectively connected to source/drain terminals of transistors in the first and second amplifying blocks in response to a control signal.

Abstract: Disclosed is a half-power buffer/amplifier. The half-power buffer/amplifier includes first and second amplifying blocks respectively corresponding to first and second channels, a first output buffer unit controlled by an output from the first amplifying block, and a second output buffer unit controlled by an output from the second amplifying block. Each of the first and second amplifying blocks includes an input unit configured to amplify a first input signal, thereby outputting first and second currents, and an amplifying unit including a first current mirror, a second current mirror, and a bias unit connected between the first current mirror and the second mirror. Nodes in the first and second amplifying blocks are selectively connected to source/drain terminals of transistors in the first and second amplifying blocks in response to a control signal.

Abstract: A mobile terminal is provided that includes a wireless communication unit configured to receive channel information and scan at least one channel, a controller configured to generate a channel database using the received channel information and generate a channel list according to a result of real time channel scanning using the channel database, and an output unit configured to display the channel list according to the result of the real time channel scanning under control of the controller.

Abstract: The present invention relates to a portable terminal including a terminal body and a retractable antenna operatively connected to the terminal body and capable of being retractably housed into and withdrawn out of the terminal body. The retractable antenna includes a base rotatably supported at the terminal body, an antenna rod connected with the base and including at least one telescoping member for extending a length of the antenna rod, and a pivot connection unit connecting the base to the antenna rod and allowing the antenna rod to pivot with respect to the base.

Abstract: The present invention relates to a portable terminal including a terminal body and a retractable antenna operatively connected to the terminal body and capable of being retractably housed into and withdrawn out of the terminal body. The retractable antenna includes a base rotatably supported at the terminal body, an antenna rod connected with the base and including at least one telescoping member for extending a length of the antenna rod, and a pivot connection unit connecting the base to the antenna rod and allowing the antenna rod to pivot with respect to the base.