Abstract: A processing-in-memory (PIM) device includes a multiplication-and-accumulation (MAC) circuit, a memory circuit, and an address pipeline circuit. The MAC circuit is configured to perform a MAC arithmetic operation or an element-wise multiplication (EWM) calculation for first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the MAC circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a zero-detection circuit and multiplier. The zero-detection circuit including first transfer gates, second transfer gates, and an output control logic circuit. The first controller and the second controller are configured to receive a first output value and a second output value generated by inverting the first output value. The first output value is having a value of “1” when all bits of the first data or the second data have a value of “0”. The output control logic circuit is configured to generate zero data including bits having a value of ‘0’ as output data of the multiplier when the second output value is a value of ‘0’.

Abstract: A processing-in-memory (PIM) device includes a multiplication-and-accumulation (MAC) circuit, a memory circuit, and an address pipeline circuit. The MAC circuit is configured to perform a MAC arithmetic operation or an element-wise multiplication (EWM) calculation for first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the MAC circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a zero-detection circuit and multiplier. The zero-detection circuit including first transfer gates, second transfer gates, and an output control logic circuit. The first controller and the second controller are configured to receive a first output value and a second output value generated by inverting the first output value. The first output value is having a value of “1” when all bits of the first data or the second data have a value of “0”. The output control logic circuit is configured to generate zero data including bits having a value of ‘0’ as output data of the multiplier when the second output value is a value of ‘0’.

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.

Abstract: A memory system may include a memory system may include a memory device including a table suitable for managing rows for an additional refresh operation; and a memory controller comprising: a replica table corresponding to the table of the memory; an error history storage circuit suitable for storing an error history of the memory device; and a determination circuit suitable for determining whether to perform an active operation of a target row to be evicted from the replica table without the additional refresh operation, using the error history, when the target row is present.

Abstract: A memory system may include a memory system may include a memory device including a table suitable for managing rows for an additional refresh operation; and a memory controller comprising: a replica table corresponding to the table of the memory; an error history storage circuit suitable for storing an error history of the memory device; and a determination circuit suitable for determining whether to perform an active operation of a target row to be evicted from the replica table without the additional refresh operation, using the error history, when the target row is present.

Abstract: A circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.

Abstract: A circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.