Patents by Inventor Mun-Heui Choi

Mun-Heui Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7582935
    Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: September 1, 2009
    Assignee: Fairchild Korea Semiconductor Ltd
    Inventors: Jong-hwan Kim, Gi-ho Cha, Mun-heui Choi, Chang-beom Jeong
  • Publication number: 20050145981
    Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.
    Type: Application
    Filed: March 4, 2005
    Publication date: July 7, 2005
    Inventors: Jong-hwan Kim, Gi-ho Cha, Mun-heui Choi, Chang-beom Jeong
  • Patent number: 6878605
    Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: April 12, 2005
    Assignee: Fairchild Korea Semiconductor Ltd
    Inventors: Jong-hwan Kim, Gi-ho Cha, Mun-heui Choi, Chang-beom Jeong
  • Publication number: 20040023443
    Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.
    Type: Application
    Filed: May 19, 2003
    Publication date: February 5, 2004
    Inventors: Jong-Hwan Kim, Gi-Ho Cha, Mun-Heui Choi, Chang-Beom Jeong
  • Patent number: 6188104
    Abstract: A trench DMOS device has a gate insulating layer on the bottom and sidewalls of the trench. The upper edges of the trench have an impurity injection region and are rounded. In addition, a first conductive layer is formed on the gate insulating layer, and a second conductive layer is formed on the first conductive layer and filled in the trench. The second conductive layer has different crystallization from the first conductive layer. As such the first conductive layer acts as a buffer between the gate insulating layer and the filled in second conductive layer. A method for fabricating a trench DMOS device includes the steps of forming an epitaxial layer on a semiconductor substrate. Then an impurity is injected into the epitaxial layer to form an impurity injection region. Then a trench is formed in the semiconductor substrate passing through the impurity injection region. Then a dry etching process is used to round the upper edges of the trench.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: February 13, 2001
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mun-Heui Choi, Dong-Soo Jeong