Abstract: The present invention relates to a networking terminal device for use in a public space, which accesses a server in connection with a communication cable installed at the public space and includes a screen and an input unit. the networking terminal device includes: a scanning element for scanning a document and an identification card to generate an electronic file; an authentication element for authenticating a user; a real-time communication element accessing the server for transmitting a file, which is generated by the scanning element and/or the authentication element, to the server; and an application element for executing a supporting business selected according to a predetermined process, wherein the elements are embedded in a housing and operated according to the control of a control unit in the housing.

Abstract: A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

Abstract: A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

Abstract: An integrated circuit memory device can include a memory cell circuit configured to store data and a sense amplifier circuit configured to sense and amplify the stored data provided as a first input to the sense amplifier circuit in comparison to a reference voltage provided as a second input to the sense amplifier circuit. A bit line electrically can be coupled to the memory cell circuit and indirectly electrically coupled to the first input of the sense amplifier circuit and configured to provide the stored data to the sense amplifier circuit. A reference voltage line can also be indirectly electrically coupled to the second input of the sense amplifier circuit and configured to provide the reference voltage to the sense amplifier circuit.

Abstract: A ferroelectric random access memory device according to the present invention includes a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

Abstract: A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

Abstract: A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

Abstract: An integrated circuit memory device can include a memory cell circuit configured to store data and a sense amplifier circuit configured to sense and amplify the stored data provided as a first input to the sense amplifier circuit in comparison to a reference voltage provided as a second input to the sense amplifier circuit. A bit line electrically can be coupled to the memory cell circuit and indirectly electrically coupled to the first input of the sense amplifier circuit and configured to provide the stored data to the sense amplifier circuit. A reference voltage line can also be indirectly electrically coupled to the second input of the sense amplifier circuit and configured to provide the reference voltage to the sense amplifier circuit.

Abstract: A nonvolatile memory device comprises a plate line driving circuit having a hierarchical word line structure. The plate line driving circuit is coupled to plate lines corresponding to a main word line. The plate line driving circuit transmits a plate line drive signal to the plate lines when the main word line is selected, and connects the plate lines to the main word line when the main word line is unselected. Therefore, a floating condition in the plate lines when the main word line is unselected can be prevented.

Abstract: A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

Abstract: A nonvolatile memory device comprises a plate line driving circuit having a hierarchical word line structure. The plate line driving circuit is coupled to plate lines corresponding to a main word line. The plate line driving circuit transmits a plate line drive signal to the plate lines when the main word line is selected, and connects the plate lines to the main word line when the main word line is unselected. Therefore, a floating condition in the plate lines when the main word line is unselected can be prevented.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

Abstract: Disclosed is a ferroelectric random access memory having a reference voltage supplying circuit with a capacitor coupling structure. The reference voltage supplying circuit including a coupling capacitor and switching transistors configured on the basis of the capacitor coupling structure. According to the reference voltage supplying circuit of the present invention, voltages on bit lines coupled to a ferroelectric memory cell and to the reference voltage supplying circuit, respectively, are simultaneously activated. Therefore, a stable sensing margin can be secured even though power noise arises during the read operation.

Abstract: Variable test voltage circuits and methods are provided for ferroelectric memory devices. The ferroelectric memory devices include a first bit line, a word line, a nonvolatile memory cell at an intersection of the first bit line and the word line, a second bit line corresponding to the first bit line and a sense amplifier connected between the first and second bit lines to sense a voltage difference between the first and second bit lines. Test circuits and methods receive a variable test voltage and force at least one of the first and second bit lines to the variable test voltage in response to control signals during a test mode of operation. The ferroelectric memory may also include a reference cell including a ferroelectric capacitor, wherein the reference cell supplies a reference voltage to the second bit line. The test circuits and methods also may be responsive to deselection of the word line to force the first bit line to the variable test voltage.