Abstract: Chip carriers having variably-sized solder pads, and integrated circuit packages incorporating such chip carriers are described. In an example, an integrated circuit package includes an integrated circuit electrically connected with a chip carrier having solder pads of different sizes. The integrated circuit may deliver high speed signals to smaller solder pads and low speed signals to larger solder pads. More particularly, the solder pads having smaller pad dimensions may better match impedance of a high speed signal line as compared to the solder pads having larger pad dimensions.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: A molded flip chip package with enhanced adhesion between mold and die backside interface and the method of fabricating the package are described. The package is less prone to mold-die delamination. In an embodiment of the invention, the package has a die with a die frontside (die bottom side) attached to a substrate and a die backside (die top side). A first material is disposed on a portion of the die backside. A second material encapsulates the first material and the die backside.

Abstract: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a first surface. The process may then include dispensing and curing an underfill material in the cavity, and attaching a lid to the first surface of the substrate.

Abstract: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a first surface. The process may then include dispensing and curing an underfill material in the cavity, and attaching a lid to the first surface of the substrate.

Abstract: A method that includes, obtaining a substrate, placing a reinforcing layer over a first side of the substrate; and thinning the substrate by removing material from an opposite side of the substrate.

Abstract: A method that includes, obtaining a substrate, placing a reinforcing layer over a first side of the substrate; and thinning the substrate by removing material from an opposite side of the substrate.

Abstract: The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

Abstract: The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.